Test Research, Inc.

Po-Shen Kuo

Hsin-Hao Chen

A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage.

Testing apparatus for providing per pin level setting

A testing apparatus with a back-drive protection function is disclosed, where the testing apparatus includes a driver and a field programmable gate array (FPGA), where the driver is electrically connected to the FPGA. The FPGA can monitor output current from the driver and perform the back-drive protection function on the driver to protect device-under-test (DUT).

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Taipei, Taiwan

Po-Shen Kuo