Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Nien Chen

Bao-Ru Young

Chih-Yung Lin

Harry-Hak-Lay Chuang

Ming Zhu

Yu-Chiun Lin

Wei Cheng Wu

Jin-Aun Ng

Chen Hua Tsai

Yi-Hsuan Chung

Chung-Chieh Yang

Chung-Peng Hsieh

Chia-Hsin Hu

Kuo-Ji Chen

Ming-Hsiang Song

Harry Hak-Lay Chuang

Hak-Lay Chuang

Chi-Hsun Hsieh

Eric Huang

Hsiao-Han Liu

Chung-Yu Chiang

Bo-Shiuan Shie

Hoppy Lee

Pei-Hsun Wu

Ming-Hung Han

Hsing-Hui Hsu

Henry Kwong

Sheng-Chen Chung

Zhen Geng

Kitchun Kwong

Taicheng Shieh

A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same

Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Integrated circuits with capacitors

A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Semiconductor device and a method of fabricating the same

A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Semiconductor device and a method for fabricating the same

A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Structure and formation method of semiconductor device with fin structures

A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.

A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Hybrid doping profile

An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Circuit incorporating multiple gate stack compositions

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Miaoli, Taiwan

Po-Nien Chen