Realtek Semiconductor Inc.

Au Optronics Corporation

Po-Lin Chen

Ying-Yen Chen

Chun-Nan Lin

Wen-Ching Tsai

Kuo-Yuan Tu

Jeong-Fa Sheu

Chun-Yi Kuo

Shu-Feng Wu

Chia-Jui Yang

Yu-Min Lin

Chih-Yuan Lin

Yu-cheng Lo

Chia-Tso Chao

Chun-teng Chen

Yueh-Shu Li

Tzung-Jin Wu

Yin-Ping Chern

Tse-Wei Wu

A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Testing circuitry for testing multicycle path circuit

A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

Semiconductor device and method for generating test pulse signals

A test circuit includes a scan chain and a wrapper chain. The wrapper chain shifts in a test pattern according a first clock. The scan chain is coupled to the wrapper chain via a logic combination of a circuit under test. The wrapper chain is configured to transmit the test pattern to the scan chain via the logic combination according to a second clock in a capture phase. The wrapper chain includes a first, a second wrapper cell, and an asynchronous register. The first wrapper cell sequentially shifts in two bits of the test pattern in the shift-in phase. The second wrapper cell shifts in the first bit of the test pattern in the shift-in phase. The asynchronous register conducts the first wrapper cell to the second wrapper cell in the shift-in phase, and latches the second wrapper cell in the capture phase.

Test circuit and test method

A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.

Scan test device and scan test method

An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Electronic device test database generating method and electronic device test database generating apparatus

A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Circuit having multiple scan modes for testing

The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Circuit testing system and circuit testing method

The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.

Test device for testing integrated circuit

A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.

Thin film transistor and method for manufacturing thereof

An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5&#xb0; to about 30&#xb0;.

Active device array substrate

A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Pixel structure, display panel, eletro-optical apparatus, and method thererof

A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

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Hsinchu, Taiwan

Po-Lin Chen