Hon Hai Precision Industry Co., Ltd.

Hong-Fu Jin Precision Industry (Shenzhen) Co., Ltd.

Ye Xin Technology Consulting Co., Ltd.

Po-Li Shih

Yi-Chun Kao

Hsin-Hua Lin

Chih-Lung Lee

Wei-Chih Chang

Kuo-Lung Fang

I-Wei Wu

I-Min Lu

Wu-Liu Tsai

Chang-Chun Wan

Chao-Chun Yang

A sensor using ultrasound to detect presence and nature of analyte includes an ultrasonic element and a receptor thereon. The ultrasonic element includes a first electrode, a second electrode facing and spaced apart from the first electrode, an insulating layer between the first electrode and the second electrode, and a vibrating film between the insulating layer and the first electrode. The vibrating film carries the first electrode. A cavity is formed between the vibrating film and the insulating layer. The receptor is on a side of the first electrode away from the second electrode. The receptor can combine with a target substance in a test analyte. When the first electrode and the second electrode are applied with different voltages, certain ultrasound frequencies are generated as the vibrating film vibrates, and the presence and weight of different target substances are indicated by the changes in resonance.

Sensor using ultrasound to detect target substance and detecting device using same

A gas sensor with instantaneous electrical response and thus detection of gas which meets it includes a substrate, a bottom gate electrode on a surface of the substrate, an insulating layer on the surface of the substrate carrying the bottom gate electrode and completely covering the bottom gate electrode. A semiconductor layer is on a surface of the insulating layer away from the substrate. Both the source electrode and the drain electrode, spaced apart, are located on a side of the semiconductor layer away from the substrate each being coupled to the semiconductor layer. The gas sensor further includes a passivation layer covering the semiconductor layer and a top gate electrode on the passivation layer, the top gate electrode being spaced from both the source and drain electrodes. The top gate electrode is made of electrically-conductive and gas-sensitive material. A method for making same is also disclosed.

Gas sensor and method for making same

A high-performance TFT substrate () for a flat panel display includes a substrate (), a first conductive layer () on the substrate (), a semiconductor layer () positioned on the first conductive layer (), and a second conductive layer () positioned on the semiconductor layer (). The first conductive layer () defines a gate electrode (). The second conductive layer () defines a source electrode () and a drain electrode () spaced apart from the source electrode (). The second conductive layer () includes a first layer () on the semiconductor layer () and a second layer () positioned on the first layer (). The first layer () can be made of metal oxide. The second layer () can be made of aluminum or aluminum alloy.

TFT substrate and method for making same

A thin film transistor array panel includes a first conductive layer () including a gate electrode; a channel layer () disposed over the gate; and a second conductive layer () disposed over the channel layer (). The second conductive layer () includes a multi-layered portion defining a source electrode () and a drain electrode (), which includes a first sub-layer (-), a second sub-layer (-), and a third sub-layer (-) sequentially disposed one over another. Both the third and the first sub-layers (--) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (-) is greater than that in the third sub-layer (-). The content ratio differentiation between the first and the third sub-layers (--) affects a lateral etch profile associated with a gap () generated in the second conductive layer () between the source and the drain electrodes (), where the associated gap () width in the third sub-layer (-) is wider than that in the first sub-layer (-).

Thin film transistor array panel and conducting structure

A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.

A semiconductor device comprises a multi-layered structure disposed over a substrate () and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (-) disposed over the substrate () and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (-) substantially defining a first indium to zinc content ratio; a middle sub-layer (-) disposed over the lower sub-layer (-) and comprising a metal material; an upper sub-layer (-) disposed over the middle sub-layer (-) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (-) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (-).

Thin film transistor array panel

A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.

Self-aligned metal oxide thin film transistor and method of making same

A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.

Array substrate and method for making same

A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.

Thin film transistor substrate, manufacturing method thereof, and liquid crystal display panel using same

A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.

Thin film transistor utilized in array substrate and manufacturing method thereof

A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.

Thin film transistor and method of manufacturing same

A display array substrate includes a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of gate connecting pads. Each gate connecting pad is disposed at an end of one of the gate lines. The end of each gate line is partly covered by a first insulation layer. The first insulation layer is an anodic oxide layer.

Display array substrate and manufacturing method thereof

An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode.

Array substrate and liquid crystal display device using same

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

Method for fabricating conducting structure and thin film transistor array panel

A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.

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Taipei, Taiwan

Po-Li Shih