United Microelectronics Corp.

Po-Kuang Hsieh

Shih-Hung Tsai

Chun-Hsien Lin

Yu-Ting Tseng

Kuan-Hao Tseng

Ching-Wen Hung

Cheng-Ping Kuo

Sheng-Yuan Hsueh

Shih-Chieh Hsu

Chih-Kai Kang

Chia-Chen Sun

Chi-Horn Pai

Chih-Chung Chen

Po-Chang Lin

Bo-Han Huang

Shu-Hsuan Chih

Chien-Ting Lin

Yu-Hsiang Lin

Po-Cheng Huang

Po-Jui Liao

Jie-Ning Yang

Yao-Chang Wang

Chi-Sheng Tseng

Kuang-Hung Huang

Shih-Chang Chang

Chueh-Fei Tai

A method for fabricating a semiconductor device includes the steps of providing a first wafer and a second wafer as the first wafer includes a device wafer and the second wafer includes a blanket wafer, bonding the first wafer and the second wafer, performing a thermal treatment process to separate the second wafer into a first portion and a second portion, and then planarizing the first portion.

Semiconductor device and method for fabricating the same

A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Nanowire transistor and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

HEMT and method of fabricating the same

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50&#xb0; C. to 100&#xb0; C., and a duration of the baking process is between 5 seconds to 120 seconds.

Rinse process after forming fin-shaped structure

A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.

Method for fabricating semiconductor device

A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.

A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

Manufacturing method of epitaxial fin-shaped structure

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.

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Kaohsiung, Taiwan

Po-Kuang Hsieh