Taiwan Semiconductor Manufacturing Comp. Ltd.

Asia Optical Co., Ltd.

Sintai Optical (shenzhen) Co., Ltd.

Po-Jen Wang

Gulbagh Singh

Tsung-Han Tsai

Kun-Tsang Chuang

Ching-Hung Kao

Chun-Ching Wu

Yao-Wen Hsu

Lin-Chen Lu

Yu-Hua Yen

Chun-Li Wu

Hsiang-Hui Tsai

Wei-Ting Chen

Hsi-Ling Chang

Ying-Hao Chen

Hung-Che Liao

Guo-Quan Lin

Ming-Huang Tseng

Guo-Yang Wu

Kern-Huat Ang

Ying-Chen Chiu

Chien-Cheng Huang

A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.

MOSFET device structure with air-gaps in spacer and methods for forming the same

A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.

LDMOS transistor and method of forming the same

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Reducing RC delay in semiconductor devices

LDMOS transistor

This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

SOI device structure for robust isolation

Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOT FETs and fully depleted SOI FETs may be provided.

Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

Semiconductor wafer with modified surface and fabrication method thereof

A lens assembly is configured to be disposed under a cover glass, in a gap region and outside a display region, including a plurality of lenses, a reflector and an image sensor. The lenses, the reflector and the image sensor are sequentially arranged from an object side to an image side along an optical axis. One of the lenses is adjacent to the object side, has a minimum diameter of clear aperture, and has an outer circumferential portion which is non-circular. The lens assembly satisfies at least one of following conditions: BFL&#x2265;VL and BFL&#x2265;0.6&#xd7;DL where BFL is a back focal length of the lens assembly, VL is a minimum side length of the image sensor, and DL is a diagonal length of the image sensor. A lens device includes a cover glass, a case, a display panel and the lens assembly.

Lens device under cover glass and lens assembly

A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

Method for forming semiconductor device structure with isolation feature

A lens device includes a lens barrel and a first lens. The lens barrel includes an object-side end. The first lens is fixed to the object-side end of the lens barrel, is configured to form an optical axis, and includes a minor diameter portion near an object side of the lens device and a major diameter portion near an image side of the lens device. The major diameter portion is connected to the minor diameter portion. A section of the first lens sectioned along the optical axis is higher at a middle portion than at both side portions. The first lens is protruded at the middle portion towards the object side to form a pillar with respect to the both side portions thereof.

Lens device

Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOI FETs and fully depleted SOI FETs may be provided.

Growing community of inventors

Taichung, Taiwan

Po-Jen Wang