United Microelectronics Corp.

Po-Jau Tsao

Chih-Yuan Hsiao

A four-transistor SRAM cell, which could be viewed as at least including two word line terminals, comprises the following elements: a first word line terminal, a second word line terminal, a first bit line terminal, a second bit line terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is coupled to the first word line terminal and the source of the first transistor is coupled to the first bit line terminal, the gate of the second transistor is coupled to the second word line terminal and the source of the second transistor is coupled to the second bit line terminal, the source of the third transistor is coupled to the drain of the first transistor and the gate of the third transistor is coupled to the drain of the second transistor, the source of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor is coupled to the drain of the first transistor. Significantly, one essential characteristic of the memory cell is that two word line terminals are used to control the state of two independent transistors separately.

Four transistor static-random-access-memory cell

A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor. Significantly, one essentially characteristic of the memory cell is two word line terminals are used to control state of two independent transistors separately.

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Taipei, Taiwan

Po-Jau Tsao