Springsoft, Inc.

Springsoft Usa, Inc.

Po-Hung Lin

Shyh-Chang Lin

Tian-Hau Tsai

Ho-Che Yu

Wei-Chung Chao

Shi-Hong Bai

A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) representation of a trial placement wherein each symmetry group and each module not included in a symmetry group is represented by a separate node of the HB*-tree. Each symmetry group node maps to a symmetry island placement for the symmetry group satisfying all symmetry and other placement constraints on the symmetry group. The placement tool employs a simulated annealing technique to iteratively perturb the HB*-tree representation to produce a sequence of trial placements, and uses a cost function to evaluate the quality of each trial placement.

Analog IC placement using symmetry-islands

A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement.

Hierarchical analog IC placement subject to symmetry, matching and proximity constraints

A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.

Analog and mixed signal IC layout system

A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and specifying a constraint on relative placement within the schematic diagram of symbols representing devices forming the pattern. The generator identifies each set of devices in the netlist that exhibits any rule's interconnection pattern as a separate 'soft group', places a constraint consistent with the rule on relative positioning within the schematic diagram of symbols representing the soft group, resolves any constraint conflicts in accordance with a constraint resolution scheme, and then places all device symbols in the schematic diagram in a manner consistent accordance with the constraints.

Rule-based schematic diagram generator

A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations of the nets. When a user requests a zoom in operation to display a smaller portion of the schematic diagram at a scale at which net representations can be viewed, the system determines routes for representations of nets that are to reside in that portion of the schematic diagram and then displays those net representations upon zooming in to that portion of the schematic diagram. When the user requests a pan operation to shift the display to another portion of the schematic diagram, the system determines routes for representations of nets that are to reside in that other portion of the schematic diagram and then displays those net representations upon panning to that other portion of the schematic diagram.

Growing community of inventors

Zhubei, Taiwan

Po-Hung Lin