Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Leadtrend Technology Corporation

Mediatek Corporation

National Yunlin University of Science and Technology

Po-Hung Chen

Shao-Yu Chou

Sung-Chieh Lin

Kuo-Ji Chen

Yu-Kai Chen

Kuoyuan Hsu

Jiann-Tseng Huang

Kuoyuan (Peter) Hsu

Subramani Kengeri

Fu-Lung Hsueh

Shine Chung

Yen-Chieh Huang

Meng-Jin Tsai

Ren-Fen Tsui

Cheng-Han Huang

Dian-Sheg Yu

Le-Tien Jung

David Yen

Shih-Guo Shen

Chin-Huang Wang

Liang Chuan Chang

Bai-Mei Chang

Wen-Kuan Fang

Cheng-Jung Hsu

Wei-Fen Pai

Chuen-Min Huang

Cheng-Yi Wu

Chang-Hsien Tai

Sheng-Kai Hsieh

Ming-Yan Fan

A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber, a hot plate disposed in the baking chamber, and a cover plate disposed over the hot plate. The cover plate has a plurality of exhaust holes. The exhaust holes include a first exhaust hole and a second exhaust hole arranged in a first direction. The first exhaust hole and the second exhaust hole have different sizes.

Photoresist baking apparatus with cover plate having uneven exhaust hole distribution

An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

Single-gate-oxide power inverter and electrostatic discharge protection circuit

A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber having an exhaust port on a sidewall of the baking chamber, a hot plate disposed in the baking chamber, an exhaust line coupled to the exhaust port, and a cover plate disposed over the hot plate and between the hot plate and the exhaust port. The exhaust line is configured to exhaust out an atmosphere inside the baking chamber in an exhaust direction. The cover plate has a plurality of exhaust holes to allow air to flow through. The exhaust holes include a first exhaust hole and a second exhaust hole arranged in a first direction that is perpendicular to the exhaust direction.

A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber, a hot plate, an exhaust line, and a cover plate. The baking chamber has an exhaust port on a sidewall thereof. The hot plate is disposed in the baking chamber and is configured to support a wafer and heat a photoresist material over the wafer. The exhaust line is coupled to the exhaust port and is configured to exhaust out the atmosphere inside the baking chamber. The cover plate is disposed over the hot plate and between the hot plate and the exhaust port. The cover plate has multiple exhaust holes to allow air to flow through. The size of one of the exhaust holes farther from the exhaust port is larger than the size of one of the exhaust holes closer to the exhaust port.

A multiple output rectifier includes a comparator-based active rectification circuit and a controller, wherein the controller is coupled to the comparator-based active rectification circuit. The comparator-based active rectification circuit is used for generating and outputting each output voltage of a plurality of output voltages according to an input voltage, the each output voltage, and a control signal corresponding to the each output voltage. The controller is used for generating the control signal according to the each output voltage and a reference voltage corresponding to the each output voltage.

Multiple output rectifier and operation method thereof

A single-inductor multiple-output (SIMO) power converter converts an input voltage into an output voltage and a biasing voltage. The SIMO power converter comprises an inductor and a primary power switch, and a control circuit. The inductor is configured for storing energy from the input voltage. The primary power switch has a control node and is connected between the inductor and the output voltage which powers an output load. The control circuit controls the primary power switch comprising an auxiliary power switch and a driver. The auxiliary power switch is connected between the inductor and the biasing voltage. The driver, powered by the biasing voltage, drives the control node. The biasing voltage determines a signal level at the control node. The primary power switch and the auxiliary power switch are controlled to distribute the energy stored in the inductor to the output voltage and the biasing voltage.

SIMO based DC-DC converters for thermoelectric energy harvesting

A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.

Electrical fuse bit cell and mask set

A method for automatically generating an image description includes following steps of: obtaining a first image data; analyzing a text file corresponding to the first image data; calculating occurrences and distribution ratios of terms, each of which contains a target word, from the text file, so as to obtain a plurality of the terms having the distribution ratios greater than a threshold; comparing the distribution ratios of the terms so as to find out at least one key term; finding out one of a plurality of lexical chains containing the key term with a greatest distribution ratio so as to generate a narrative language chain; and setting the narrative language chain as a description of the first image data. A system for automatically generating an image description and a non-volatile computer-readable storage media are also disclosed.

Non-volatile computer-readable storage media, system and method for automatically generating image description

In at least one embodiment, a method includes applying an input voltage external to a semiconductor chip to a first circuit of the semiconductor chip to generate an output voltage external to the semiconductor chip. The first circuit is electrically coupled to a resistive device. A logic state of the resistive device is determined based on a logic state of the external output voltage.

Measuring electrical resistance

A cache controller, a method for controlling the cache controller, and a computing system comprising the same are provided. The computer system comprises a processor and a cache controller. The cache controller is electrically connected to the processor and comprises a first port, a second port, and at least one cache. The first port is configured to receive an address of a content, wherein a type of the content is one of instruction and data. The second port is configured to receive an information bit corresponding to the content, wherein the information bit indicates the type of the content. The at least one cache comprises at least one cache lines. Each of the cache lines comprises a content field and corresponding to an information field. The content and the information bit is stored in the content field of one of the cache lines and the corresponding information field respectively according to the information bit and the address. Thereby, instruction and data are separated in a unified cache.

Cache controller, method for controlling the cache controller, and computing system comprising the same

An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

Voltage level shifter

A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

Growing community of inventors

Taipei, Taiwan

Po-Hung Chen