Industrial Technology Research Institute

Elite Semiconductor Microelectronics Technology Inc.

Elite Semiconductor Memory Technology, Inc

Po-Hsun Wu

Jen-Shou Hsu

Chien-Yi Lee

Yi-Ying Lin

Shih-Je Shiu

Tsung-Yu Yang

Che-Wei Hsu

Jen-Ji Wang

Chien-Chih Liao

Cheng-Wei Wang

Chin-Ming Chen

Chun-Ting Chen

Meng-Chiou Liao

Ya-Chun Lai

Chang-Lin Wang

Tsung-Yi Bai

Yu-Sheng Tseng

Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.

Method and circuit for adaptive column-select line signal generation

A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

Method for self-calibrating tDQSCK that is skew between rising edge of memory clock signal and rising edge of DQS signal during read operation and associated signal processing circuit

A processing path generating method includes the following steps. An image-capturing device is moved to the first position of the region of interest to perform an image-capture on a workpiece, so as to obtain a first image. The image-capturing device is moved to a second position to perform the image-capture on the workpiece, so as to obtain a second image. A first edge characteristic and a second edge characteristic of the workpiece are obtained according to the first image and the second image. Three-dimensional edge information of the workpiece is fitted according to the first edge characteristic and the second edge characteristic. A processing path is generated according to the three-dimensional edge information.

Processing path generating method and device

A dodge method of machining path and a machining system is provided. By inserting a flag into an original machining path, an interference between the flag and a suction cup of a support unit is determined. A coding instruction is inserted at the interference to edit the original machining path, thereby generating an edited machining path. Therefore, when a machining equipment executes the edited machining path, the support unit may smoothly dodge a knife of the machining equipment.

Dodge method of machining path and machining system

A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.

Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device

A contour accuracy measuring system and a contour accuracy measuring method are provided. The contour accuracy measuring system captures location coordinate data of shafts of a machine tool. The location coordinate data are calculated to obtain a first true round trajectory on an inclined plane as reference information. The contour accuracy measuring system then adjusts parameters of the locations of the shafts based on the location coordinate data of the shafts of the reference information to generate a second true round trajectory on the inclined plane, so as to get to know whether the locations of the shafts after the parameters are adjusted comply with a standard. Therefore, the overall measurement process can be speeded up by automatically measuring the parameters and automatically testing an operating status.

Contour accuracy measuring system and contour accuracy measuring method

A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.

Data first-in first-out (FIFO) circuit

A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.

Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit

A backlash automatic detection system comprises a control device and a machine tool. The machine tool comprises a servo driver, a lead screw, a nut seat and a platform. The method comprises: entering an initial state and outputting a control command to the servo driver through the control device; driving the lead screw by the servo driver to move the nut seat towards a first direction and changing the movement direction of the nut seat towards a reverse second direction by the servo driver; defining a backlash phenomenon period according to one time point at which the nut seat starts to move towards the second direction and another time point at which the platform is driven to move by the nut seat; defining the displacement of the nut seat corresponding to the backlash phenomenon period as a backlash value.

Backlash automatic detection system for machine tool and method using the same

A machining assistance method and an apparatus using the same are provided. The machining assistance method comprises following steps. Firstly, a circle correction path is received for driving a platform to perform a circular motion. Next, a driving torque of the server driver driving the platform is obtained. Then, whether the driving torque is changed to 0 is determined; if yes, a first position of the platform is recorded. Then, whether the driving torque is changed to a peak is determined; if yes, a second position of the platform is recorded. After that, the server driver is controlled to drive the platform according to a first position and a second position in a machining process.

Machining assistance method and the apparatus using the same

An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.

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Hsinchu, Taiwan

Po-Hsun Wu