Realtek Semiconductor Inc.

Po-Hsien Wu

Huan-Wen Chen

Li-Yu Chen

Tien-Hung Lin

Yi-Chen Tseng

Yu-Pin Lin

Tzu-Min Yeh

Wei-Chieh Liu

Shi-Xuan Hong

Yun-Hung Lin

A method for reading and writing frame images with multiple buffer blocks and a system are provided. In the system, when an input-fast mode is switched to an input-low mode, a read end decides whether to read a next buffer block according to a writing progress. If a write end does not change the buffer block to be written, the read end keeps reading the buffer block, and otherwise the read end selects a next buffer block to be read. In an instance that the read end is required to read the same frame image repeatedly, when the input-slow mode is switched to the input-fast mode, the write end decides whether to write a next buffer block according to a reading progress. The write end selects a next buffer block to be written with a next frame image if the read end already reads last buffer block.

Method for reading and writing frame images with multiple buffer blocks and system

An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.

Image processing method and image processing device for enhancing image processing efficiency

A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.

Transmission control system of multi-media signal, transmitter control circuit and receiver control circuit

A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Signal transmission device and related method

A signal processing method for maintaining a signal relative relationship and an electronic device thereof are provided. The signal processing method includes: detecting that a current input period of a vertical synchronization signal changes relative to a previous input period; determining whether a frequency difference between a pulse width modulation signal and the vertical synchronization signal is within an acceptable range, and when the frequency difference is not within the acceptable range, performing a frequency adjustment stage to adjust a period of the pulse width modulation signal to be close to the current input period; selectively performing a phase adjustment stage to adjust a phase of the pulse width modulation signal to a phase of the vertical synchronization signal; and maintaining a relative phase relationship between the pulse width modulation signal and the vertical synchronization signal.

Signal processing method for maintaining signal relative relationship and electronic device thereof

A video processing method for a video processing circuit includes receiving a first video source corresponding to a first pixel rate and a second video source corresponding to a second pixel rate, wherein a processing data rate of a video processing path is greater than or equal to a sum of the first pixel rate and the second pixel rate. The method further includes using the processing data rate to sequentially perform an image processing to a first image of the first video source and a second image of the second video source corresponding to the same display time, to generate a first processed image and a second processed image.

Video processing circuit and method for handling multiple videos using single video processing path capable of increasing processing data rate and saving circuit area

A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.

First in and first out apparatus and driving method thereof

The present invention discloses an image processing circuit including an image processing unit, a frame rate adjusting circuit and a phase detection and control circuit. In operations of the image processing circuit, the image processing unit is configured to process an input image signal including a plurality of frames to generate a processed image signal including a plurality of processed frames, the frame rate adjusting circuit is configured to adjust a row number of vertical blanking intervals of at least one of the processed frames according to a control signal, to generate an output image signal including at least one adjusted frame, and the phase detection and control circuit is configured to determine a phase relationship of the input image signal or the processed image signal and the output image signal to generate the control signal.

Image processing circuit and image processing method

A clock switching apparatus is provided. The clock input terminal receives a first clock signal as an input clock signal at first and start to receive a second clock signal as the input clock signal during a masking state of a masking signal within a clock-switching time period. The enabling synchronizing circuit receives a clock-switching enabling signal, receives the input clock signal and generate a synchronized enabling signal accordingly. The masking circuit receives the synchronized enabling signal and the mask signal to generate a final enabling signal. The output circuit receives the input clock signal, receive the final enabling signal that disables the output circuit only when either the masking signal is at the masking state or the synchronized enabling signal is at the clock-switching enabling state, and generate an output clock signal according to the input clock signal when the output circuit is enabled.

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Hsinchu, Taiwan

Po-Hsien Wu