Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Po-Hao Tseng

Feng-Min Lee

Ming-Hsiu Lee

Yu-Hsuan Lin

Yu-Yu Lin

Kai-Chieh Hsu

Tian-Cih Bo

Dai-Ying Lee

Wen-Ting Chu

Erh-Kun Lai

Yu-Wen Liao

Yong-Shiuan Tsair

Chieh-Fei Chiu

Chin-Yu Mei

Jenn-Gwo Hwu

Wei-Cheng Tian

Yun-Yuan Wang

Yung-Chun Li

Cheng-Hsien Lu

Chao-Hung Wang

Liang-Yu Chen

Shao Yu Fang

Wei-Lun Weng

Wei-Fu Wang

A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.

Memory structure, manufacturing method thereof, and operating method thereof

A high-level architecture for 3D-NAND based in-memory search provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. A search word is presented to a 3D-NAND memory along a direction of a bit line of the 3D-NAND memory. Each character of the word comprises a number of digits. Each digit is matched against respective layers of the 3D-NAND memory. Each digit is usable to represent one of a plurality of levels according to a selected encoding. Optionally, various lengths of words are accommodated via serial and/or parallel operations of one or more 3D-NAND memories.

High-level architecture for 3D-NAND based in-memory search

An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

In memory searching device

A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

Non-volatile 3D memory search architecture

A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.

Memory device and in-memory search method thereof

An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders

A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

Universal memory for in-memory computing and operation method thereof

A memory device is provided. The memory device includes channel layers, word lines, memory layers disposed between the channel layers and the word lines, and memory cells defined at cross-points of the channel layers and the word lines. The memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n. In the first operation, a first electric field is produced in a portion of the memory layers. The word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field.

Memory device and method for operating the same

The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

IMS memory cell, IMS method and IMS memory device

A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

Hyperdimensional computing device

A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Memory device having two memory stacks over one bottom electrode

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

Ternary content addressable memory and decision generation method for the same

A memory cell and a memory device are provided. The memory cell comprises: a write transistor; and a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data; wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable.

Memory cell and memory device thereof

A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.

A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

Growing community of inventors

Taichung, Taiwan

Po-Hao Tseng