Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Po-Hao Tsai

Jing-Cheng Lin

Shin-Puu Jeng

Po-Yao Chuang

Li-Hui Cheng

Techi Wong

Chen-Hua Douglas Yu

Jui-Pin Hung

Meng-Liang Lin

Ming-Da Cheng

Yi-Wen Wu

Ming-Chih Yew

Der-Chyang Yeh

Shuo-Mao Chen

Cheng-Lin Huang

Meng-Wei Chou

An-Jhih Su

Po-Yao Lin

Shih-Ting Hung

Ting-Li Yang

Chi-Hsi Wu

Feng-Cheng Hsu

Szu Wei Lu

Ying Ching Shih

Shang-Yun Hou

Ying-Ching Shih

Wen-Hsiung Lu

Cheng-Chieh Hsieh

Chia-Kuei Hsu

Chiung-Han Yeh

Yi-Jou Lin

Li-Hsien Huang

Ming-Shih Yeh

Wei-Yu Chen

Mirng-Ji Lii

Kuo-Ching Hsu

Hsu-Lun Liu

Ta-Wei Liu

I-Ting Chen

Porter Chen

Wen-Chih Chiou

Szu-Wei Lu

Ching-Wen Hsiao

Chin-Fu Kao

Yuh-Wen Lee

Hong-Seng Shue

Tzy-Kuang Lee

Yung-Han Chuang

Hsueh-Sheng Wang

Chen-Shien Chen

Hsin-Yu Chen

Jung-Hua Chang

Hsien-Wen Liu

Chih-Chien Pan

Song-Bor Lee

Fang Wen Tsai

Chien-Chen Li

Kai-Di Wu

Sheng-Pin Yang

Kai-Hsiang Yen

Yan-Fu Lin

Yi-Hang Lin

Nai-Hao Kuo

Hao-Chun Liu

Jing-Hung Chiou

Su-Fei Lin

Wen-Che Chang

Ya-Hsi Hwung

Wu Sen Chiu

Wen-Jiun Liu

Neng-Chieh Chang

Wei-Hung Lin

Tsung-Fu Tsai

Hui-Min Huang

Chih-Hsien Lin

Li-Chung Kuo

Shih-Ting Lin

Chang-Jung Hsueh

Hua-Wei Tseng

Kuan-Hung Chen

Hsien-Ju Tsou

Yung-Sheng Lin

Chen-Hsuan Tsai

Wei-yu Chen

Hao Chun Liu

Yu-Tse Su

Hung-Wei Tsai

Long-Hua Lee

Shih-Yung Peng

Jeh-Yin Chang

Yi Chou

A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.

Chip package structure with conductive shielding film

A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip over the redistribution structure. The package structure also includes an adhesive element over the semiconductor chip. Opposite outermost edges of the adhesive element are laterally between opposite outermost edges of the redistribution structure. The package structure further includes a protective layer laterally surrounding the semiconductor chip and the adhesive element. In addition, the package structure includes a thermal conductive element over the semiconductor chip. The thermal conductive element is surrounded by the adhesive element.

Package structure with adhesive element over semiconductor chip

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Redistribution lines having nano columns and method forming same

A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

Semiconductor device and method of manufacture

A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

Hybrid micro-bump integration with redistribution layer

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

Semiconductor device and method

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.

Methods of packaging semiconductor devices and packaged semiconductor devices

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same

A semiconductor package is provided. The semiconductor package includes a redistribution structure, a semiconductor die, and an interposer structure. The interposer structure includes an insulating base having a first surface facing the semiconductor die and a second surface opposite to the first surface and conductive features formed over the insulating base. The conductive features include first portions on the first surface of the insulating base and vertically overlapping the semiconductor die, second portions on the first surface of the insulating base and located outside a projection area of the semiconductor die in a top view, third portions on the second surface of the insulating base and vertically overlapping the semiconductor die, and fourth portions on the second surface of the insulating base and located outside the projection area of the semiconductor die in the top view. The interposer structure includes capping layers and dielectric features.

Semiconductor package with improved interposer structure

A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Fan-out package with controllable standoff

A semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.

Semiconductor package structure comprising via structure and redistribution layer structure

A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Method of manufacture overlay mark using laser marking process for semiconductor device

Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Dummy structure of stacked and bonded semiconductor device

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Zhongli, Taiwan

Po-Hao Tsai