Mediatek Corporation

National Taiwan University

Institute for Information Industry

Po-Han Wang

Chia-Lin Yang

Yu-Jung Cheng

Cheng-Hsuan Li

A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.

Method for managing a last level cache and apparatus utilizing the same

The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Growing community of inventors

Taipei, Taiwan

Po-Han Wang