Industrial Technology Research Institute

National Applied Research Laboratories

Po-Han Huang

Chih-Wei Liu

Chein-Wei Jen

Tay-Jyi Lin

I-Tao Liao

Keng-Yu Lin

Wei-Xiang Tang

Chih-Wei Hsu

Shing-Wu Tung

Ting-Ming Huang

Shenq-Tsong Chang

Chi Lung Wu

Wei-Sheng Huang

Chan-Hao Chang

Hsien-Ching Hsieh

Che-Yu Liao

Chie-Min Chao

Chuan-Cheng Peng

Pi-Chen Hsiao

Chia-Yen Chan

Kuo-Cheng Lee

A voltage compensation circuit and a control method thereof dynamically compensate a voltage drop caused by supplying power from a first power line to a function circuit. The voltage compensation circuit includes an amplifier, a detection module and a boosting module. The amplifier has an inverting input end coupled to the first power line and the function circuit to be supplied with a load voltage supplying to the function circuit, a non-inverting input end for being supplied with a reference voltage, and an output end coupled to the detection module to output a comparison signal. The boosting module is coupled between the detection module and the inverting input end of the amplifier. The detection module generates compensation voltage information according to the comparison signal. The boosting module outputs the compensation voltage to the inverting input end of the amplifier according to the compensation voltage information.

Voltage compensation circuit and control method thereof

A non-violate memory device and a control method thereof are provided. The non-violate memory device includes a flip-flop, a retention cell and a memory cell. The flip-flop includes an output inverter. The flip-flop generates a second data according to a first data and a retention signal. The retention cell is coupled to the output inverter of the flip-flop. The retention cell temporarily stores the second data when the retention signal is enabled. During the period that retention signal is enabled, the memory cell stores the second data temporarily stored by the retention cell. Thus, another operation mode of the non-violate memory device is provided to save more power.

Non-volatile semiconductor memory device with temporary data retention cells and control method thereof

The present invention discloses a system and method for nondestructively measuring the refractive index and the central thickness of a lens. The system comprises a radius measurement module arranged for measuring the curvature radius of the first surface of the lens; a focus measurement module arranged for measuring the best focus distance of the first surface of the lens; and a calculation module arranged for performing the first or the second calculation process according to the lensmaker's formula. Wherein, when the central thickness is given, the calculation module performs the first calculation process according to the curvature radius, the best focus distance and the central thickness to calculate the refractive index. On the contrary, when the refractive index is given, the calculation module performs the second calculation process according to the curvature radius, the best focus distance and the refractive index to calculate the central thickness.

System and method for nondestructive measuring refractive index and thickness of lens

A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package.

Very long instruction word (VLIW) processor with power management, and apparatus and method of power management therefor

A system and a corresponding method for multi-core synchronous debugging of a multi-core platform including a plurality of cores are provided. The method includes the following steps. Transmit a core debugging instruction to one of the cores selected by a system debugging instruction or store a group setting included in the system debugging instruction according to the type of the system debugging instruction. Control every core in a group to start executing program instructions simultaneously according to another system debugging instruction. The group is a subset of the cores and the group setting indicates which ones of the cores are included in the group. Use a handshaking mechanism to control all cores of the group to enter a debug mode simultaneously when a debug event happens in any core of the group.

System and method for multi-core synchronous debugging of a multi-core platform

A method and corresponding apparatus for compiling high-level languages into specific processor architectures are provided. In this embodiment, the specific processor is encapsulated in a virtual processor interface with simple instruction set architecture, and a compiler translates application programs into corresponding assembly codes. Further, the difficulty of the compiler design is reduced.

Method and corresponding apparatus for compiling high-level languages into specific processor architectures

A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping-pong register providing exclusively accessible data storage, and a public register file. The public register file comprises at least two read ports, each coupled to a function unit, providing read accessibility for the function units, and one write port to write data to the public register file.

Digital signal processor

A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer

An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

Growing community of inventors

Zhubei, Taiwan

Po-Han Huang