Industrial Technology Research Institute

Opto Tech Corporation

Po-Chun Yeh

Lung-Han Peng

Jeng-Wei Yu

Heng-Yuan Lee

Yu-De Lin

Hsin-Yun Yang

Po-Ting Lee

Chih-Yao Wang

Chuan-Wei Tsou

Yao-Te Wang

Chia-Ming Chang

Chih-Ming Lai

Heng-Yin Chen

Yi-Keng Fu

Pei-Jer Tzeng

Hung-Pin Shih

Hsueh-Hsing Liu

Wei-Yen Lee

Tsu-Min Liu

Kan-Hsueh Tsai

Yung-Ming Lin

Yung-Hsiang Chiu

Hsien-Yi Liao

Yao-Cing Han

Haw-Tyng Huang

Chen-Yen Lin

Han-Chieh Ho

Po-Tsung Tu

Chien-Hua Hsu

Jung-Tse Tsai

An all-oxide transistor structure includes a substrate having an upper surface and a first transistor disposed on the upper surface of the substrate. The first transistor includes a first drain, a first dielectric layer, a first source, at least one first opening and a first channel layer. The first drain, the first dielectric layer and the first source are disposed on the substrate along a first direction, and the first direction is parallel to a normal direction of the upper surface. The first opening passes through the first drain, the first dielectric layer and the first source along the first direction. The first channel layer, the first gate dielectric layer and the first gate are disposed in the first opening. The first gate dielectric layer is disposed on the first channel layer. The first gate is disposed on the first gate dielectric layer.

All-oxide transistor structure, method for fabricating the same and display panel comprising the structure

A ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer. The ferroelectric composite layer includes a first electrode layer, a second electrode layer, a ferroelectric layer and an antiferroelectric layer. The first electrode layer is opposite to the second electrode layer, and the ferroelectric layer and the antiferroelectric layer are disposed between the first electrode layer and the second electrode layer.

Ferroeolectric memories with ferroelectric composite layer

A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

Ferroelectric memories

A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of () or (), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of () or (), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of ().

A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.

An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

Enhancement mode gallium nitride based transistor device and manufacturing method thereof

This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 &#x3bc;m and a height between 1 and 500 &#x3bc;m.

Structure of epitaxial wafer and method of fabricating the same

A III-nitride based semiconductor structure includes a substrate; a buffer layer disposed above the substrate; a first gallium nitrite (GaN) layer disposed above the buffer layer and including p-type GaN; a second GaN layer disposed on the first GaN layer and including at least a first region and a second region; a channel layer disposed above the second GaN layer; a barrier layer disposed above the channel layer; and a gate electrode disposed above the barrier layer. The first region of the second GaN layer is positioned correspondingly to the gate electrode and includes n-type GaN having a first doping concentration. The second region of the second GaN layer (such as the lateral portion of the second GaN layer) is positioned correspondingly to the areas outsides the gate electrode and includes n-type GaN having a second doping concentration larger than the first doping concentration.

III-nitride based semiconductor structure

A white LED chip includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first material layer, the active layer includes a second material layer, and the second barrier layer includes a third material layer. The N-type layer is disposed over the tunneling structure. An energy gap of the second material layer is lower than an energy gap of the first material layer and an energy gap of the third material layer. Each of the first material layer, the second material layer and the third material layer is a metal oxide layer, a metal nitride layer or a metal oxynitride layer.

White LED chip and white LED packaging device

A flexible display and a controlling method thereof are provided. The flexible display includes a plurality of pressure sensors, a display unit and a processing unit, wherein the processing unit is connected to the pressure sensors and the display unit. The processing unit obtains pressure values from each of the pressure sensors within a time unit and generates a pressure area and a pressure variance according to the pressure values from each of the pressure sensors. The processing unit further determines a display mode of the display unit according to the pressure area and the pressure variance. Therefore, the flexible display is capable of providing several kinds of display mode only based on the equipped pressure sensors.

Flexible display and method for controlling the flexible display

A white LED is provided. The white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first metal oxide layer. The active layer includes a second metal oxide layer. The second barrier layer includes a third metal oxide layer. The N-type layer is disposed over the tunneling structure. The N-type electrode and the P-type electrode are respectively contacted with the N-type layer and the P-type layer. An energy gap of the second metal oxide layer is lower than an energy gap of the first metal oxide layer and is lower than an energy gap of the third metal oxide layer.

White LED

Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Method of selective photo-enhanced wet oxidation for nitride layer regrowth on substrates and associated structure

Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a semiconductor structure may comprise: a first substrate structure; a III-nitride structure bonded with the first substrate structure; a plurality of air gaps formed between the first substrate structure and the III-nitride structure; and a III-oxide layer formed on surfaces around the air gaps, wherein a portion of the III-nitride structure including surfaces around the air gaps is transformed into the III-oxide layer by a selective photo-enhanced wet oxidation, and the III-oxide layer is formed between an untransformed portion of the III-nitride structure and the first substrate structure.

Method of separating nitride films from growth substrates by selective photo-enhanced wet oxidation and associated semiconductor structure

An embodiment of a print signal generation system is provided. The system comprises a sensor, a divisor processing unit, a reference signal generator, and a print trigger signal generator. The sensor detects a first offset of a first location of a medium being printed. The divisor processing unit generates a first divisor according to the first offset and a predetermined divisor. The reference signal generator generates a reference signal. The print trigger signal generator generates a print trigger signal according to the first divisor and the reference signal.

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Taichung, Taiwan

Po-Chun Yeh