United Microelectronics Corp.

Po-Chun Yang

Cheng-Tung Huang

Yi-Ting Wu

Jen-Yu Wang

Yung-Ching Hsieh

Jian-Jhong Chen

Bo-Chang Li

Jhen-Siang Wu

Yan-Jou Chen

Chun-Hsien Huang

Yu-Tse Kuo

Shu-Ru Wang

Chun-Yen Tseng

Chang-Hung Chen

Chia-Wei Lee

Hsin-Chih Yu

Chih-Wei Tsai

Ya-Lan Chiou

Zong-Sheng Zheng

A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

MRAM circuit structure and layout structure

A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Sense amplifier circuit with temperature compensation

A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Bottom-pinned spin-orbit torque magnetic random access memory and method of manufacturing the same

A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.

Magnetic memory device having shared source line and bit line

In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.

Magnetoresistive random-access memory

A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

Layout pattern for magnetoresistive random access memory

A memory includes (n&#x2212;1) non-volatile cells, (n&#x2212;1) bit lines and a current driving circuit. Each of the (n&#x2212;1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n&#x2212;1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n&#x2212;1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n&#x2212;1) non-volatile cells.

Memory including non-volatile cells and current driving circuit

A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.

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Tainan, Taiwan

Po-Chun Yang