Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Epistar Corporation

Po-Chun Liu

Chung-Yi Yu

Chi-Ming Chen

Chia-Shiung Tsai

Chen-Hao Chiang

Xiaomeng Chen

Yih-Der Guo

Ru-Liang Lee

Han-Chin Chiu

Jenq-Dar Tsay

Min-Chang Ching

Kuei-Ming Chen

Eugene I-Chun Chen

Chih-Ming Lai

Chih-Ming Chen

Ming Chyi Liu

Ming-Feng Shieh

Lee-Chuan Tseng

Yu-Hsien Lin

Han-Wei Wu

Jin-Dah Chen

Stan Chen

Jen-Cheng Liu

Yung-Chang Chang

Yi-Shin Chu

Kuan-Chieh Huang

Hsiang-Lin Chen

Yin-Kai Liao

Sin-Yi Jiang

Eugene Chen

Jyh-Ming Hung

Chu-Li Chao

Chung-Chieh Hsu

King-Yuen Wong

Chih-Wen Hsiung

Hung-Ta Lin

Ho-Yung David Hwang

Chun-Kai Lan

Chin-Cheng Chang

Wen-Yueh Liu

Ming-Chang Ching

Min-Hsun Hsieh

Jiun-Lei Jerry Yu

Chen Ou

Wen-Huang Liu

Yao-Chung Chang

Tzu-Feng Tseng

Tung-Wei Chi

A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.

Surface uniformity control in pixel structures of image sensors

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Source/drains in semiconductor devices and methods of forming thereof

Various embodiments of the present disclosure are directed towards a method for forming an image sensor in which a device layer has high crystalline quality. According to some embodiments, a hard mask layer is deposited covering a substrate. A first etch is performed into the hard mask layer and the substrate to form a cavity. A second etch is performed to remove crystalline damage from the first etch and to laterally recess the substrate in the cavity so the hard mask layer overhangs the cavity. A sacrificial layer is formed lining cavity, a blanket ion implantation is performed into the substrate through the sacrificial layer, and the sacrificial layer is removed. An interlayer is epitaxially grown lining the cavity and having a top surface underlying the hard mask layer, and a device layer is epitaxially grown filling the cavity over the interlayer. A photodetector is formed in the device layer.

Method for forming an image sensor

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Passivation layer for epitaxial semiconductor process

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Manufacturing method of semiconductor device

A high electron mobility transistor (HEMT) includes a substrate; and a first semiconductor layer over the substrate. The HEMT further includes a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium. The HEMT further includes a top layer over the second semiconductor layer. The HEMT further includes a gate electrode over the top layer. The HEMT further includes a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.

High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

In some embodiments, a method for forming a semiconductor device is provided. The method includes etching a substrate to form a recess within a surface of the substrate. An epitaxial material is formed within the recess, a capping structure is formed on the epitaxial material, and a capping layer is formed onto the capping structure. The capping layer laterally extends past an outermost sidewall of the capping structure. Dopants are implanted into the epitaxial material. Implanting the dopants into the epitaxial material forms a first doped region having a first doping type and a second doped region having a second doping type.

Capping structure to reduce dark current in image sensors

Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

Dielectric sidewall structure for quality improvement in Ge and SiGe devices

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

Growing community of inventors

Hsinchu, Taiwan

Po-Chun Liu