Mediatek Corporation

Young Lighting Technology Corporation

Po-Chun Huang

Yu-Li Hsueh

Chao-Ching Hung

Yuan Chen

Wei-Kun Su

Ang-Sheng Lin

Chien-Wei Chen

Chiao-Chih Yang

Juei-Ting Sun

Wei-Hao Chiu

Pang-Ning Chen

Chih-Hsien Shen

Shuo-Jen Hsu

Yu-Hsien Chang

Wen-Hsien Chiu

Pi-An Wu

Tzu-Wei Han

Hsin-Tse Tsai

Hsiu-Hsien Ting

Hsuan-An Lin

Tzu-Wen Sung

Disclosed herein are devices and methods to reduce unwanted CIM3 emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.

Apparatus and methods for improved transmit power

A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.

Fractional-N phase-locked loop and sliced charge pump control method thereof

A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.

Frequency multiplier and delay-reused duty cycle calibration method thereof

A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

Method for startup of crystal oscillator with aid of external clock injection, associated crystal oscillator and monitoring circuit therein

A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.

Fast-locking phase-locked loop and associated fast-locking method thereof

A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.

Magnetically pumped voltage controlled oscillator

The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.

Charge pump having level-shifting mechanism

A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.

Quadrature clock generating mechanism of communication system transmitter

A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.

Voltage controlled oscillator and control method thereof

A communications apparatus is provided. A radio module transmits first packets before establishing a connection with a peer communications device. A transmission power utilized for transmitting the first packets is adjustable, so that multiple levels of transmission power are utilized for transmitting the first packets.

Communications apparatuses and method for multi-level transmission power control thereof

A backlight module includes a back plate, a light guide plate, a heat insulation layer, a heat dissipation member, and a light source device. The back plate has a first surface, a second surface opposite to the first surface, and an opening passing through the back plate. The light guide plate is disposed on the first surface, the heat insulation layer is disposed on the second surface, and the heat dissipation member is disposed on the heat insulation layer. The light source device is connected to the heat dissipation member and protrudes from the first surface to face the light guide plate through the opening.

Backlight module with heat dissipation structure

An apparatus used in a communication system having a plurality of time slots includes a signal processing circuit, a signal detector, and a controlling circuit. The signal processing circuit receives an input signal. The signal detector detects the input signal to generate a detection result. The controlling circuit controls the signal processing circuit according to the detection result. When the detection result does not meet a predetermined criterion, the controlling circuit adjusts the signal processing circuit for reducing power consumption of the signal processing circuit.

Growing community of inventors

Hsinchu, Taiwan

Po-Chun Huang