National Taiwan University

Phison Electronics Corporation

Faraday Technology Corporation

Po-Chun Hsieh

Tzi-Dar Chiueh

Yun-Chieh Chen

Fu-Yi Tsai

Wen-Ching Hsiung

Zeh-Yang Chew

I-Chung Tsai

Shou-Chih Lee

A memory storage device having a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a power management circuit and a memory control circuit unit is provided. When an external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device via the second connection interface unit, supplies an operation voltage to the rewritable non-volatile memory module and the memory control circuit unit and supplies the second power supply voltage to a host device. When the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit receives a first power supply voltage from the host device via the first connection interface unit and supplies the operation voltage to the memory control circuit unit and the rewritable non-volatile memory module.

Memory storage device and power management method thereof

ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.

ESD protection circuit with EOS immunity

A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.

Low-power delay buffer circuit

Growing community of inventors

Kaohsiung, Taiwan

Po-Chun Hsieh