Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Chun Chiu

Tse-Hua Lu

Kai-Ling Chiu

Ping-Fang Hung

Yu-Kuo Cheng

Yuichiro Yamashita

Hsin-Chi Chen

Yung-Lung Hsu

Ching-Hung Kao

Chia-Yu Wei

Fu-Cheng Chang

Chia-Pin Cheng

Chin-Hsun Hsiao

Yu-Hsuan Cheng

Che-Chun Lu

Masayuki Uchiyama

Ching-Ling Cheng

A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.

Implantation process for semiconductor device

An image sensor including a substrate, a trench isolation, a plurality of image sensing units, at least one phase detection unit, and an interconnection layer is provided. The trench isolation is in the substrate, and a plurality of active areas of the substrate are separated from each other by the trench isolation. The image sensing units and the at least one phase detection unit are in the active areas arranged in an array, and a sensing area of the at least one phase detection unit is smaller than a sensing area of each of the image sensing units. The interconnection layer is disposed on the image sensing units and the at least one phase detection unit. In addition, a method of fabricating an image sensor is also provided.

Image sensor and method for manufacturing the same

An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.

Methods for measuring the full well capacity of CMOS image sensors

This disclosure provides pixel arrays made up of a clear pixel and a color pixel. The color pixel includes a first photo-detecting element and a color pixel access transistor to selectively couple the first photo-detecting element to a first charge-storage node. The clear pixel includes a second photo-detecting element and a clear pixel access transistor to selectively couple the second photo-detecting element to a second charge-storage node. The color pixel access transistor transfers a first charge per unit time between the first photo-detecting element and the first charge-storage node. The clear pixel access transistor transfers a second charge per unit time between the clear pixel access transistor and the second charge-storage node. The first charge per unit time is less than the second charge per unit time to mitigate blooming. In other embodiments, the clear pixel includes an excess-charge transfer path that couples the clear pixel to a DC supply node to mitigate blooming.

Pixel array with clear and color pixels exhibiting improved blooming performance

Growing community of inventors

Taipei, Taiwan

Po-Chun Chiu