Realtek Semiconductor Inc.

Powerchip Semiconductor Corporation

National Yang Ming Chiao Tung University

Po-Ching Lin

Tay-Her Tsaur

Hsin-Cheng Hsu

Yu-Cheng Yang

Ying-Dar Lin

Chung-Yu Huang

Shih-Hsin Liao

Jyun-Ren Chen

Yuan-Cheng Lai

Cheng-Jui Chen

Cheng-Ying Wu

Ming-Dao Liu

The present invention discloses an electrostatic discharge protection circuit having time-extended discharging mechanism. A RC circuit is coupled between an ESD input terminal that receives an ESD input and a ground terminal and includes an input control terminal. An inverter includes a P-type transistor coupled between the ESD input terminal and an output control terminal and an N-type transistor circuit including N-type transistors coupled in series and between the output control terminal and a ground terminal, wherein two of the N-type transistors has an internal connection terminal. Gates of the P-type transistor and N-type transistors are controlled by the input control terminal. A switch transistor is coupled between the ESD input terminal and the internal connection terminal. A discharging transistor is coupled between the ESD input terminal and the ground terminal. The gates of the switch transistor and the discharging transistor are controlled by the output control terminal.

Electrostatic discharge protection circuit having time-extended discharging mechanism

An electrostatic discharge protection circuit includes a voltage drop circuit, a detector circuit, and a clamping circuit. The voltage drop circuit is configured to generate a second voltage according to a first voltage. The second voltage is smaller than the first voltage. The detector circuit is coupled to the voltage drop circuit. The detector circuit is configured to generate a control signal according to the second voltage and an input voltage. The clamping circuit is coupled to the voltage drop circuit and the detector circuit. The clamping circuit is configured to provide an electrostatic discharge path according to a voltage level of the control signal.

Electrostatic discharge protection circuit and operation method

The present invention discloses an electrostatic discharge protection circuit having false-trigger prevention mechanism. A RC circuit, including an input control terminal, is coupled between an electrostatic discharge input terminal for receiving an input power and a ground terminal. An inverter includes a P-type transistor circuit, including P-type transistors coupled between the electrostatic discharge input terminal and an output control terminal in series and having an internal connection terminal between two of the P-type transistors, and an N-type transistor, coupled between the output control terminal and the ground terminal. Gates of the P-type and N-type transistors are controlled by the input control terminal A switch transistor, having the gate controlled by the input control terminal, is coupled between the internal connection terminal and the ground terminal. A discharging transistor having the gate controlled by the output control terminal, is coupled between the electrostatic discharge input terminal and the ground terminal.

Electrostatic discharge protection circuit having false-trigger prevention mechanism

A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.

Semiconductor device

An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N&#x2212;1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N&#x2212;1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.

Electrostatic discharge protection device and electrostatic discharge detector circuit

Disclosed is a transmission gate circuit including a control voltage generating circuit, a high voltage transmission circuit and a low voltage transmission circuit. The high and low voltage transmission circuits are coupled between an input terminal and an output terminal. The control voltage generating circuit generates two voltage groups according to an input voltage of the input terminal and an enable voltage and thereby controls the high and low voltage transmission circuits with the two voltage groups respectively. When the enable voltage is high, one voltage group includes identical voltages while a difference between any of the identical voltages and any voltage of the other voltage group is not higher than a predetermined voltage; when the enable voltage is low, each voltage group includes decremental voltages. The high/low voltage transmission circuit is turned on when the enable voltage is high and the input voltage is high/low.

Transmission gate circuit

Disclosed is an inverter capable of withstanding a high voltage. The inverter includes a control voltage generating circuit, a high voltage transmission circuit, and a low voltage transmission circuit. The control voltage generating circuit generates a first group of control voltages and a second group of control voltages according to an input voltage, in which one group includes decrement voltages and the other group includes identical voltages. The high/low voltage transmission circuit is coupled between a high/low voltage terminal and an output terminal, wherein when the input voltage is low/high, the high/low voltage transmission circuit is turned on according to the first/second group of control voltages so that an output voltage of the output terminal is equal to a high/low voltage of the high/low voltage terminal.

Inverter with control voltage generating circuit capable of withstanding high voltage

An ESD protection device includes a detection circuit and a clamping circuit. The detection circuit is configured to output a first control signal and a second control signal according to a first voltage and a second voltage that is different from the first voltage, in which if an ESD event occurs, the detection circuit is configured to perform an inverse operation according to the second voltage, in order to generate the first control signal and the second control signal. The clamping circuit is configured to be turned on according to the first control signal and the second control signal, in order to provide a discharging path for a current associated with the ESD event.

Electrostatic discharge protection device, detection circuit and protection method thereof

A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.

Voltage level shifter circuit

The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.

Buffer circuit

A network communication system, a software-defined network controller and a routing method thereof are provided. The routing method is adapted to the software-defined network controller. The routing method includes the following steps: determining a first root switch corresponding to at least one first service cluster according to service chaining information, wherein each of the at least one first service cluster includes at least one service node for providing a first service; determining first routing path information for routing a packet flow from a first target switch to the first root switch; and configuring first group entry information for the first root switch according to cluster information of the at least one first service cluster, wherein the first group entry information is for performing a first routing path selection of the packet flow corresponding to the first service by the first root switch.

Network communication system, software-defined network controller and routing method thereof

An electrostatic discharge (ESD) protection circuit is disclosed, which comprises an ESD detection circuit and protection switches. If an ESD event occurs, the ESD detection circuit turns off the protection switches so as to protect an application circuit provided in integrated circuits (IC) from being damaged by the electrostatic discharge, and if not, the ESD detection circuit turns on the protection switches so as to make the application circuit provided in integrated circuits (IC) function normally.

Electrostatic discharge protection circuit

An apparatus for positioning a transport system and a load port is described, including a signal emitting unit disposed on the transport system and a positioning board on the load port. The signal emitting unit has two positioning points thereon capable of emitting two light beams to the positioning board, while the positioning board has two holes thereon at two positions corresponding to the two positioning points. The two light beams can pass through the two holes perpendicular to the positioning board in a horizontal state when the load port is aligned with the transport system.

Positioning apparatus and positioning method using the same

A process for removing particles from a reticle is described, wherein the process is performed by using a pellicle particle detector (PPD) and a particle removing tool disposed in front of the PPD as well as fixed to the PPD. The particle removing tool includes at least one gas spray member directed toward a surface of the reticle for removing particles. The process includes steps as follows, step (a) loading the reticle into the PPD through the gas spray member to detect whether the reticle has particles thereon; step (b) ejecting the reticle from the PPD; step (c) turning on the particle removing tool as well as going back to step (a) when particles are detected on the reticle, and ending the particle removal process when no particle is detected on the reticle.

Process for removing particles from reticle

A tool and a process for removing particles from a reticle are described. The tool is disposed in front of a pellicle particle detector, including at least a gas spray member toward a surface of the reticle for removing particles and a supporting member supporting the gas spray member in front of the pellicle particle detector. The supporting member can further fix the tool onto the pellicle particle detector. In the particle removing process, when particles are detected on the reticle, the tool is turned on and the reticle is loaded into the pellicle particle detector through the gas spray member in order to remove the particles from the reticle before the pellicle particle detector detects the particles.

Growing community of inventors

Hsinchu, Taiwan

Po-Ching Lin