United Microelectronics Corp.

Po-Ching Chuang

Chih-Wei Hsu

Chih-Chung Wang

Wen-Fang Lee

Ming-Tsung Lee

Cheng-Hua Yang

A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

High voltage metal-oxide-semiconductor transistor device and layout pattern thereof

A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.

Growing community of inventors

Taoyuan County, Taiwan

Po-Ching Chuang