Marvell International Limited

Marvellworld Trade Ltd.

Po-Chien Chang

Chee Hoe Chu

Wei Zhou

Saeed Azimi

Ping Zheng

Gang Wang

Sehat Sutardja

Roawen Chen

Embodiments of the present invention provide a method comprising performing an operation on a first flash drive of a plurality of flash drives configured in a parallel flash drive architecture, wherein the operation occupies a flash controller corresponding to the first flash drive, sending a signal to a processor coupled with the parallel flash drive architecture to indicate that the flash controller is occupied, and writing data to two or more of the plurality of flash drives, other than the first flash drive, by striping the data amongst the two or more of the plurality of flash drives in response to the signal to the processor. Other embodiments may be described and/or claimed.

Operation aware striping in parallel drives

This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer.

Preloading an application while an operating system loads

An emulation circuit configured to emulate each of a master mode and a slave mode to provide an interface between a host device and a plurality of storage devices. The emulation circuit includes a first bus and a second bus. The emulation circuit includes a plurality of bridge circuits each configured to communicate with the host device over the first bus, communicate with a respective storage device of a plurality of storage devices over the second bus, and receive a mode select signal configured to set the bridge circuit to one of a host mode and a device mode. The bridge circuit is further configured to, if the mode select signal sets the bridge circuit to the host mode, select, based on an emulation select signal, between the master mode and the slave mode.

Method and apparatus for providing an interface between a host device and a plurality of storage devices

In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component.

Serial interface for FPGA prototyping

A flash controller includes a PCIe interface, a DMA engine module, a memory control module, and a flash control module. The PCIe interface communicates with a host device and receives first data from the host device. The first data is formatted using a native PCIe protocol and includes a first key-value pair that is to be stored in first memory. The first memory includes flash memory. The first key-value pair includes a first unique number and the first data. The PCIe interface receives second data from the first memory and transmits the second data from the host device. The second data is formatted using the native PCIe protocol and includes a second key-value pair. The second key-value pair includes a second unique number and the second data. The DMA engine module transfers the first and second data between the PCIe interface, the first memory and second memory.

Data storage methods and apparatus

An integrated circuit ('IC') may have flash memory circuitry associated with it. The IC may also have controllable routing circuitry for routing signal information (1) between the flash memory circuitry and any one of a plurality of signal ports of the IC, or (2) between various ones of those signal ports. Multiple instance of such ICs and their associated flash memory circuitries may be connected to one another via the above-mentioned signal ports to provide flash memory storage systems of any size in which data can be routed in and out at least partly via the controllable routing circuitries of the various ICs.

Multiple port routing circuitry for flash memory storage systems

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.

Systems and methods for operating a flash memory file system

A peripheral device includes a host interface, a power interface, a switch, a control module, and a regulator. The host interface transfers data between the peripheral device and a host. The power interface receives power from a power source. The power source is separate from the peripheral device and the host. The control module monitors the host interface and generates a control signal to transition the switch from a first state to a second state when the host interface does not receive an expected signal from the host. The regulator powers the control module and a circuit of the peripheral device based on the power received from the power source. The control module is separate from the circuit. The switch activates the control module, the regulator and the circuit when in the first state and deactivates the control module, the regulator and the circuit when in the second state.

Power smart peripheral devices with external power supplies

A serializer/deserializer for a network device includes a data module configured to generate parallel data and side band data. A serializer is configured to convert the parallel data to serialized data for transmission over a communication channel, wherein the serialized data includes a serial data waveform. A side band transmission module is configured to generate a clock signal, inject the clock signal with side band data to generate a modulated clock signal, and apply the modulated clock signal to the serialized data to generate a modified serial data waveform. The modified serial data waveform includes the serialized data and the side band data and includes pulses with an increased pulse width and/or a decreased pulse width with respect to the serial data waveform. The serializer is configured to transmit, over the communication channel, the modified serial data waveform including the serialized data and the side band data.

System and method for side band communication in SERDES transmission/receive channels

A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-state memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.

Solid-state disk with wireless functionality

Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash controller in communication with the cache memory and the flash memory; wherein the flash controller of a first one of the flash modules is configured to operate the cache memories together as a global cache; wherein the flash controller of a second one of the flash modules is configured to operate a second one of the flash modules as a directory controller for the flash memories.

Systems and methods for operating a plurality of flash modules in a flash memory file system

A system for controlling a storage device. A semiconductor chip of the storage device, includes a first memory. The first memory corresponds to a first type of memory, is configured to perform random access memory functions, and is not configured to perform direct memory access functions. A second memory external to the semiconductor chip is configured to interface with the semiconductor chip. The second memory corresponds to a second type of memory that is different than the first type of memory, is configured to perform direct memory access functions, and is not configured to perform random access memory function. The second memory includes a memory cell and an interface configured to interface between components of the second memory including the memory cell and the semiconductor chip.

Memory architecture and system, and interface protocol

Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal.

Spread-spectrum clock acquisition and tracking

A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network.

Growing community of inventors

Saratoga, CA, United States of America

Po-Chien Chang