Taiwan Semiconductor Manufacturing Comp. Ltd.

Omnivision Technologies, Inc.

Po-Chia Lai

Stefan Rusu

Chi-Lin Liu

Meng-Hung Shen

Jerry Chang-Jui Kao

Yan-Hao Chen

Wen-Hao Chen

Kuo-Ji Chen

Wun-Jie Lin

Yu-Ti Su

David Barry Scott

Rabiul Islam

Shu-Yi Ying

Kuan-Te Li

Jiann-Tyng Tzeng

Ting-Wei Chiang

Jung-Chan Yang

Shang-Wei Fang

Hui-Zhong Zhuang

Lee-Chung Lu

Jerry Chang Jui Kao

Min Liu

Charles Qingle Wu

Wei-Ling Chang

Wei-Ren Chen

Greg Gruber

Ming-Chang Kuo

Meng-hung Shen

Chun-Yen Lee

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

Low-power flip flop circuit

An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Method and system for latch-up prevention

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.

Flip flop circuit

An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.

Methods of resistance and capacitance reduction to circuit output nodes

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. In one aspect, the semiconductor device includes a plurality of deep trench capacitors and a plurality of via contacts that at least partially surround the deep trench capacitors. Variations may be made to the number and locations of the plurality of via contacts such that design requirements for the packaging are satisfied.

Semiconductor device including deep trench capacitors and via contacts

Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

Metal-insulator-metal capacitors and methods of forming the same

An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.

A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Multiple fin count layout, method, system, and device

A flip-flop circuit using AOI and OAI includes: a MUX unit with a multiplexer selecting between a first signal and a second signal; a master unit with two OAI, wherein the first OAI is coupled between a first node Nand a third node N, the second OAI is coupled between a second node Nand a fourth node N; a slave unit with two AOI, wherein the first AOI is coupled between the third node Nand a fifth node N, the second AOI is coupled between the fourth node Nand a sixth node N; and a clock for controlling the two AOI and the two OAI, the clock is connected to the first and the second AOI and the first and the second OAI.

Low-power AOI-based flip-flop

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Fremont, CA, United States of America

Po-Chia Lai