United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Po-Cheng Huang

Yu-Ting Li

Kun-Ju Li

Fu-Shou Tsai

Chih-Hsun Lin

Chia-Lin Hsu

Wen-Chin Lin

Teng-Chun Tsai

Yi-Liang Liu

Wu-Sian Sie

Chang-Hung Kung

Yen-Ming Chen

Jen-Chieh Lin

Chun-Wei Hsu

Chun-Tsen Lu

Jie-Ning Yang

Li-Chieh Hsu

Chun-Liang Liu

Yi-Wei Chen

Chien-Ting Lin

Chih-Chien Liu

Shih-Fang Tzou

Chun-Yuan Wu

Yi-Wen Chen

Po-Jui Liao

Chien-Nan Lin

Ren-Peng Huang

Chun-Hsiung Wang

I-Lun Hung

Chan-Lon Yang

Po-Chao Tsao

Chen-Yi Weng

Chen-Ming Huang

I-Ming Tseng

Jing-Yin Jhang

Sheng-Yuan Hsueh

Kuo-Chih Lai

Hsin-Fu Huang

Shui-Yen Lu

Shih-Chieh Hsu

Rai-Min Huang

Zhi-Cheng Lee

Che-Hua Hsu

Yu-Shu Lin

Min-Chuan Tsai

Cheng-Guo Chen

Yu-Wen Wang

Chih-Kai Kang

Ching-I Li

Chia-Chen Sun

Chi-Horn Pai

Po-Kuang Hsieh

Shao-Hua Hsu

Kuo-Chin Hung

Yao-Chang Wang

Guang-Yaw Hwang

Rung-Yuan Lee

Chi-Sheng Tseng

Tzung-Ying Lee

Tsung-Lung Tsai

Ya-Jyuan Hung

Wei-Jen Wu

Hsin-Chih Yu

Tzu-Hsiang Hung

Hung-Ling Shih

Jung-Tsung Tseng

Jia-Feng Fang

Kuang-Hung Huang

Shih-Chang Chang

Yen-Liang Lu

Jian-Wei Chen

Shu-Hsuan Chih

Shih-Ming Lin

Yue-Han Wu

Chia-Hsi Chen

Chia-His Chen

Lan-Ping Chang

Chih-Jung Su

A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Method for forming semiconductor integrated circuit structure

Semiconductor integrated circuit structure

A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

Planarization method

The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

Wafer polishing pad and using method thereof

Semiconductor integrated circuit structure and method for forming the same

A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

Method of fabricating a gate cap layer

A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

Method for forming semiconductor structure

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

Method for planarizing material layer

A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.

Method for manufacturing metal interconnects

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Method for fabricating semiconductor device

A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Method for manufacturing semiconductor device with a barrier layer having overhung portions

A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.

Manufacturing method of semiconductor device

A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Method of forming target patterns

A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Method of forming semiconductor device

A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Semiconductor process

Growing community of inventors

Kaohsiung, Taiwan

Po-Cheng Huang