Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Cheng Chen

Chien-Hao Chen

Chung-Chiang Wu

Hsien-Ming Lee

Kuo-Chan Huang

Chi On Chui

Hung-Chin Chung

Wei-Chin Lee

Pin-Hsuan Yeh

Chen-Chi Huang

Chang-Yao Huang

Chih-ming Tsao

Deng-an Wang

A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

Polyimide profile control

A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Selective hybrid capping layer for metal gates of transistors

A system for processing a semiconductor wafer is provided. The system includes a processing tool. The system also includes gas handling housing having a gas inlet and a gas outlet. The system further includes an exhaust conduit fluidly communicating with the processing tool and the gas inlet of the gas handling housing. In addition, the system includes at least one first filtering assembly and at least one second filtering assembly. The first filtering assembly and the second filtering assembly are positioned in the gas handling housing and arranged in a series along a flowing path that extends from the gas inlet to the gas outlet of the gas handling housing. Each of the first filtering assembly and the second filtering assembly comprises a plurality of wire meshes stacked on top of another.

Particle removal method in semiconductor fabrication process

A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Gate resistance reduction through low-resistivity conductive layer

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Jiaoxi, Taiwan

Po-Cheng Chen