United Microelectronics Corp.

Mediatek Corporation

Po-Chao Tsao

Ming-Tsung Chen

Chia-Jui Liang

Chih-Sen Huang

Ching-Wen Hung

Ming-Te Wei

Chien-Ting Lin

Shih-Fang Tzou

Chang-Chi Huang

Shih-Fang Hong

En-Chiuan Liou

Feng-Yi Chang

Chieh-Te Chen

Jia-Rong Wu

Yu-Hsiang Hung

Jiunn-Hsiung Liao

Pei-Yu Chou

Ying-Chih Lin

Yu-Lan Chang

Chih-Wen Feng

Yi-Yiing Chiang

Jun-Jie Wang

Chia-Wei Huang

Ching-Ling Lin

Ling-Chun Chou

Lung-En Kuo

Chien-Yang Chen

Chung-Ju Lee

Yi-Wei Chen

Ssu-I Fu

Chi-Mao Hsu

Ming-Jui Chen

Chien-Ming Lai

Chung-Fu Chang

Kuan-Yang Liao

Chia-Wen Liang

Chao-Ching Hsieh

Cheng-Guo Chen

Chen-Hua Tsai

Chih-Ning Wu

Hui-Ling Chen

Shin-Chuan Huang

Tzung-Yu Hung

Chia-Jung Li

Wen-Chen Wu

I-Ming Tseng

Chia-Lin Hsu

Hsien-Hsin Lin

Shu-Ru Wang

Yu-Hua Huang

Po-Cheng Huang

Shin-Chi Chen

Yu-Ting Li

I-Chang Wang

Ching-Li Yang

Tsung-Hung Chang

Wu-Sian Sie

Yao-Hung Huang

Yi-Liang Liu

Jun-Chi Huang

Guan-Kai Huang

Chun-Hsiung Wang

Cheng-Yen Wu

Yun-San Huang

Shuen-Cheng Lei

Chia-Yu Yang

Hsi-Hua Liu

Chin-Wei Lin

Yu-Lin Yang

Chia-Chun Sun

Chih-Min Lin

A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature according to the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures according to the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer according to the DVS block target temperature.

Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing process

A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device. The back-side gate contact is formed passing through the insulator layer and electrically connected to the gate structure of the isolation field-effect transistor device.

Semiconductor structure and method for forming the same

A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

Semiconductor structure with buried power rail, integrated circuit and method for manufacturing the semiconductor structure

A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

Semiconductor structure and method of forming the same

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

Semiconductor component and manufacturing method thereof

The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.

Method of making semiconductor structure having contact plug

A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.

Semiconductor integrated circuit

A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Semiconductor device having metal gate and manufacturing method thereof

The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

Manufacturing method for forming semiconductor structure with sub-fin structures

A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Semiconductor process

A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and a plurality of first protecting fins surrounding the active region. Each of the plurality of active fins extends along a first direction and includes a first length along the first direction. The plurality of first protecting fins extend along the first direction. One of the plurality of first protecting fins immediately adjacent to the active region has a second length along the first direction, and the second length is longer than the first length.

Semiconductor integrated device including FinFET device and protecting structure

The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Shallow trench isolation in bulk substrate

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Taipei, Taiwan

Po-Chao Tsao