Synopsys, Inc.

Plamen A Asenov

Victor Moroz

Salvatore Maria Amoroso

Xi-Wei Lin

David Thomas Reid

Zudian Qin

Binjie Cheng

Andrew John Pender

Andrew R Brown

Jaehyun Lee

Manuel Aldegunde Rodriguez

A method of forming a multitude of GAAFETs on a silicon substrate includes forming alternating layers of Si nanosheets and SiGe alloys above the silicon substrate, depositing a layer of oxide buffer above the top layer of SiGe alloy, depositing a mask layer above the oxide buffer layer, patterning the mask and the oxide, and performing a RIE of the silicon nanosheet and SiGe alloy layers so as to form tapered pillars of silicon nanosheet and SiGe alloy layers. In each tapered pillar, a width of the first layer of silicon nanosheet that is closer to the substrate is greater than a width of the etched second layer of silicon nanosheet that is formed above the first layer of silicon nanosheet. The first, and second tapered silicon nanosheet layers in each pillar form channels of first and second GAAFETs.

Stacked nanosheet device for process and performance optimization

A configuration to isolate ion implantation of silicon channels for placement of integrated circuit devices within an integrated circuit layout. The configuration layers a photolithographic mask having one or more openings on a silicon substrate. The configuration directs a focused ion beam towards the silicon substrate to implant ions in the silicon substrate at the one or more openings in the photolithographic mask. The configuration anneals the silicon substrate with the layered photolithographic mask to activate a reaction between silicon of the silicon substrate and the implanted ion to achieve an ionized formation in the silicon substrate.

Isolating ion implantation of silicon channels for integrated circuit layout

A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line. A first word line is connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates. A second word line is connected to gate conductors of the first and second pMOS pass gates in the first and second transmission gates.

CFET SRAM cell utilizing 8 transistors

The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Dynamic random-access memory pass transistors with statistical variations in leakage currents

Growing community of inventors

Glasgow, United Kingdom

Plamen A Asenov