Intel Corporation

Piyush N Desai

Hong Wang

Perry H Wang

Per H Hammarlund

Milind Baburao Girkar

Xiang Chris Zou

Xinmin Tian

John P Shen

John Thomas Shen

Quinn W Merrell

Cameron B McNairy

Ayman G Abdo

Madhu S Athreya

Keith A Drescher

Steve Shih-wei Liao

Richard J Glass

William R Greene

Ashok N Seshadri

Anthony N Mah

Ravi K Chandran

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Programmable event driven yield mechanism which may activate other threads

A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

User-programmable low-overhead multithreading

A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.

Method, apparatus and system for facilitating debug for link interconnects

Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

Microprocessor design support for computer system and platform validation

A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.

Growing community of inventors

Pleasanton, CA, United States of America

Piyush N Desai