Microsoft Technology Licensing, LLC

Piyush Abhay Hatolkar

Alexander Lyakhov

Juan Pablo Munoz Constantine

Anant Shankar Deval

Charles Walter Boecker

Maya Subhadra

Asad Azam

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

Synchronization of integrated circuit dies that contain a processor and clock generator by adjusting delay lines based on phase count

Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Efficient system on chip power delivery with adaptive voltage headroom control

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Hillsboro, OR, United States of America

Piyush Abhay Hatolkar