Micron Technology Incorporated

Pitamber Shukla

Scott Anthony Stoller

Robert W Mason

Giuseppina Puzzilli

Niccolo' Righetti

Priya Venkataraman

Ching-Huang Lu

Fulvio Rori

Steven Michael Kientz

Niccolo′ Righetti

Chi Ming Chu

Sandeep Reddy Kadasani

Kenneth William Marr

Devin M Batutis

Anita Marguerite Ekren

Jiun-Horng Lai

Justin Bates

Tarun Singh Yadav

Bin Wang

Hossein Afkhami

Kishore Kumar Muchherla

Yoshiaki Fukuzumi

Zhenming Zhou

Giuseppe Cariello

Murong Lang

Chiara Cerafogli

Vipul Patel

Avinash Rajagiri

Ekamdeep Singh

Ronit Roneel Prakash

Chengkuan Yin

Phani Raghavendra Yasasvi Gangavarapu

Attila A Herrera

Wai Ying Lo

Qun Su

A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

Dynamic block categorization to improve reliability and performance in memory sub-system

Memory cells may store multiple bits per cell. For example, three-level cell (TLC) memory stores three bits per cell using eight voltage levels. The number of memory cells at each voltage is approximately the total number of cells divided by the number of voltage levels. The number of memory cells above a certain read voltage is the CFByte value for the read voltage. Based on a difference between the CFByte value and a target CFByte value for the read voltage, an adjustment value is determined. Characteristics of an individual memory device may be determined by finding several CFByte values for a small range of read voltages. Using the gathered CFByte values, a DAC adjustment value is determined for the individual memory device.

Charge loss tracking through targeted bit count

Aspects of the present disclosure configure a memory sub-system controller to adaptively allocate word lines (WLs). The controller accesses reliability data of a set of main WLs of a block of the set of memory components. The controller determines that one or more WLs of the set of main WLs of the block are associated with respective reliability data that transgress a threshold and, in response to determining that the one or more WLs are associated with the respective reliability data that transgress the threshold, replaces the one or more WLs of the set of main WLs of the block with one or more dummy WLs. The controller programs data into the block using the one or more dummy WLs instead of the one or more WLs of the set of main WLs of the block.

Dynamic word line allocation in memory systems

Methods, systems, and apparatuses include determining a read counter for a portion of memory of a memory device satisfies a read threshold. A weighted subportion identifier for the portion of memory is selected in response to the read counter satisfying the threshold. The weighted subportion identifier is selected probabilistically, a probability of selection based on defectivity information for subportions of memory of the portion of memory. A subportion of memory is determined using the weighted subportion identifier. A data validity scan is performed on the subportion of memory.

Probabilistic data integrity scans using risk factor estimation

A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Low stress refresh erase in a memory device

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.

Determining read voltage offset in memory devices

Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.

Memory systems with flexible erase suspend-resume operations, and associated systems, devices, and methods

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.

Managing defective blocks during multi-plane programming operations in memory devices

Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

Memory system failure detection and self recovery of memory dice

Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

Read calibration by sector of memory

Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

Memory operation based on block-associated temperature

Prioritization of Vscans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of Vscans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

Dynamic prioritization of selector Vscans

A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

Adaptive erase pulse width modulation based on erase suspend during erase pulse ramping period

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

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Boise, ID, United States of America

Pitamber Shukla