Maxim Integrated Products, Inc.

Globalfoundries U.S. Inc.

Bedrock Automation Platforms Inc.

Roche Sequencing Solutions, Inc.

I.clarity Innovations LLC

Polybiomics, Inc.

Village Experts, Inc.

Roche Diagnostics Gmbh

F. Hoffmann-la Roche Ag

Pirooz Parvarandeh

Venkatesh P Gopinath

Christopher Francis Edwards

Albert Rooyakkers

James G Calvin

Nicole Dorene Kerness

Arkadii V Samoilov

Anand K Chamakura

David Skurnik

Nevzat Akin Kestelli

Ilya K Veygman

Sunny Kweisun Hsu

Geoffrey A Barrall

Joy T Jones

Peter R Harper

Viren V Khandekar

Sung Ung Kwak

Khanh Tran

Anthony S Partow

Licheng Niu

Bipul C Paul

Anthony Stephen Doy

Arvin Emadi

John S Foster

Navneet Jain

Robert Michael Muchsel

Kenneth Allen Honer

David Bingham

Oliver Peter King-Smith

Edward Tangkwai Ma

Mandana Veiseh

Cheng-Wei Pei

Reynante Tamunan Alvarado

Todd S Rutherford

Amit Subhash Kelkar

Jason Komadina

Donald Wood Loomis, Iii

S Bahram Bahrami

Chiung C Lo

Halid Mulaosmanovic

Sui Ping Shieh

Charlotte Yang

Farook Afsari

Marowen Ng

Wing Kei Au

Takeshi Harada

Abhishek Sahasrabudhe

Altanai Bisht

Timothy Scott Edward Hiller

Satish Dhote

Ronald L Cicero

Guojun Chen

Richard Wilenken

Terry Martin

Bobak Parvarandeh

Violet Parvarandeh

Periyapatna G Venkatesh

Aaron Peter Schellenberg

Geoffrey Barrall

Wing Au

Kenneth A Honer

A method of forming a plurality of lipid bilayers over an array of cells in a nanopore based sequencing chip is disclosed. Each of the cells comprises a well. A first salt buffer solution with a first osmolarity is flowed over a cell in the nanopore based sequencing chip to substantially fill a well in the cell with the first salt buffer solution. A lipid and solvent mixture is flowed over the cell to deposit a lipid membrane over the well that encloses the first salt buffer solution in the well. A second salt buffer solution with a second osmolarity is flowed above the well to reduce the thickness of the lipid membrane, wherein the second osmolarity is a lower osmolarity than the first osmolarity such that an osmotic imbalance is created between a first volume inside the well and a second volume outside the well.

Osmotic imbalance methods for bilayer formation

Techniques for replacing nanopores within a nanopore based sequencing chip are provided. A first electrolyte solution is added to the external reservoir of the sequencing chip, introducing an osmotic imbalance between the reservoir and the well chamber located on the opposite side of a lipid bilayer membrane. The osmotic imbalance causes the membrane to change shape, and a nanopore within the membrane to be ejected. A second electrolyte solution is then added to the external reservoir to provide replacement nanopores and to restore the membrane shape. The replacement nanopores can be inserted into the membrane, effectively replacing the initial pore without causing the destruction of the membrane.

Removing and reinserting protein nanopores in a membrane using osmotic imbalance

A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements connected between input nodes and a bitline. Each memory element includes a programmable resistor with an input connected to an input node and an output connected to the bitline. Each bank includes a feedback buffer connected to the bitline and an output node. Output nodes of banks in the same column are connected to the same column interconnect line. The initial bank in each row includes amplifiers connected between the input nodes and the memory elements, respectively. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.

Partitioned memory architecture with single resistor memory elements for in-memory serial processing

Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Non-volatile static random access memory bit cells with ferroelectric field-effect transistors

A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

Partitioned memory architecture and method for repeatedly using the architecture for multiple in-memory processing layers

Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements

A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

Partitioned memory architecture with single resistor or dual resistor memory elements for in-memory pipeline processing

A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements, each including first and second programmable resistors having inputs connected to an input node and outputs connected to first and second bitlines. In each bank, first and second feedback buffers are connected to the first and second bitlines and first and second output nodes. First and second output nodes of banks in the same column are connected to the same first and second column interconnect lines. The initial bank in each row includes amplifiers connected between the input nodes and memory elements. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.

Partitioned memory architecture with dual resistor memory elements for in-memory serial processing

Circuits that include resistive memory elements and methods of using such circuits to generate a physical unclonable function. The circuit includes a first resistive memory element, a second resistive memory element, a first transistor having a source/drain region connected to the first resistive memory element, and a second transistor having a source/drain region connected to the second resistive memory element. The circuit further includes a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

Physical unclonable functions based on a circuit including resistive memory elements

An exercise equipment has a structure that can be easily collapsed for storage, and that provides improved utility due to its multiple functional capabilities and configurations thereby enabling a comprehensive set of strength exercises. The exercise equipment includes a rigid base structure that can be folded into compact form when not in use and can be configured for accessories that attach to the base structure. The exercise equipment with attached accessories combines heretofore separate pieces of equipment into one that covers a fraction of the floor space of all such separate pieces of equipment. This provides exercise equipment that is more flexible, more functional, and has a smaller footprint, all of which can be folded up for compact storage.

Exercise equipment

A diaper wetness detection system includes a diaper, a wetness sensor, an RFID unit, and a transceiver unit. The RFID unit is a battery-less device that receives an interrogation signal transmitted by the transceiver unit. The RFID unit or the transceiver unit are configured to determine if a measurable characteristic, as sensed by the wetness sensor, indicates if the diaper is wet. The measurable characteristic can be a voltage or current indicative of a resistance, capacitance, or impedance at an area sensed by the wetness sensor. The value of the measurable characteristic is different when the diaper is wet versus dry. Comparing the measurable characteristic value to a threshold value or to one or more previously sensed measurable characteristic values enables a determination to be made as to whether or not the diaper is wet. The RFID unit can be detachably coupled to the diaper for simple attachment and removal.

Diaper with electronic wetness detection

Toward forming a single hybrid biosensing-imaging system that can operate inside an incubator, structures and methods are directed to placing modular and removable biosensors and biocompatible interfaces in 3D transparent test wells that contain biological samples. The technology enables continuous monitoring of multiple simultaneous parameters and functions of a living cell or cell clusters such as alterations of cellular ligands, physicochemical biomarkers, phenotypes, and/or extracellular compositions upon interactions with analytes or during progressions. Methods of capturing and analyzing direct orthogonal information from biological samples in 2D and 3D, which are conducive to generating new insights are presented.

Orthogonal polybiosensing and imaging systems

Growing community of inventors

Los Altos Hills, CA, United States of America

Pirooz Parvarandeh