Ncr Corporation

Pirmin L Weisser

Edward C King

Fulps V Vermeer

Jackson L Ellis

Robert B Moussavi

Forrest O Arnold

A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.

Computer memory system having programmable operational characteristics

A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

Memory system with write buffer, prefetch and internal caches

A method and system for managing data elements in a memory system. The memory system is accessible by a plurality of bus masters connected by a bus to the system. Code data elements to be read are predicted. The predicted code data elements are then transferred within the memory system from a slow to high speed memory without delaying memory access requests for data from the bus masters.

System and method for enhancing computer operation by prefetching data

A method and system for transferring data elements from a computer main memory to a cache memory. The main and cache memories are accessible by a host processor and other bus masters connected thereto by a bus. Code data elements to be read by the host processor are predicted. The predicted code data elements are then transferred from the main memory to cache memory without delaying memory access requests for data from the other bus masters.

System and method for prefetching data from a main computer memory into

A method for reading a multiple byte data element stored in both first and second memories. Selected bytes of the data element are invalidated in the first memory. Valid bytes from the first memory are combined with remaining bytes from the second memory in response to a read request.

Growing community of inventors

Unterkirnach, Germany

Pirmin L Weisser