Intel Corporation

Piotr Majcher

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Mark Jay Charney

Zeev Sperber

Jesus Corbal

Amit Gradstein

Simon Rubanovich

Milind Baburao Girkar

Galina Ryvchin

Georg Stemmer

Joachim Hofer

Josef G Bauer

Piotr Rozen

Lukasz M Malinowski

Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.

Systems, apparatuses, and methods for addition of partial products

Systems, apparatuses, and methods for fused multiply add

In some embodiments, packed data elements of first and second packed data source operands are of a first, different size than a second size of packed data elements of a third packed data operand. Execution circuitry executes decoded single instruction to perform, for each packed data element position of a destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.

A computer-implemented method of speech recognition comprises forming a weighted finite state transducer (WFST) having nodes associated with states and interconnected by arcs, and to identify at least one word or word sequence hypothesis, identifying multiple sub-graphs on the WFST, each sub-graph having the same arrangement of multiple states and at least one arc, and propagating tokens in parallel through the sub-graphs, where each sub-graph is stored as a supertoken each having an array of tokens.

System and method of automatic speech recognition using parallel processing for weighted finite state transducer-based speech decoding

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Straszyn, Poland

Piotr Majcher