Arm Limited

Piotr Chrobak

Michal Bogusz

Daren Croxford

Damian Modrzyk

Damian Piotr Modrzyk

Sharjeel Saeed

Ozgur Ozkurt

Kushan Vijaykumar Vyas

Tomasz Jan Pabis

Michal Golek

Pawel Duc

An apparatus for providing a foreground frame to be composited with a background frame in a chroma-keying arrangement, each of the foreground frame and the background frame comprising one or more regions that together form the respective frame. A detection module determines whether each frame region has a predetermined colour value and generates and stores chroma keying information based on the determination. Control circuitry then controls image processing to be performed on the region according to the stored chroma keying information.

Method of and apparatus for processing frames in a data processing system

A display controllercomprises a first display processing corecomprising a first input stageoperable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stageoperable to provide an output surface for display to a first display, and a second display processing corecomprising a second input stageoperable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stageoperable to provide an output surface for display to a second display. The display controlleralso comprises an internal data pathfor passing pixel data of an output surface from the second display coreto the first display core

Display controller

A data processing system includes a scaleroperable to scale a received input data array to provide a scaled output version of the input data array. When it is desired to produce a de-interlaced and scaled output version of an input data array, the input data arrayis provided to the scaler, and the scalerscales the input data arrayso as to simultaneously de-interlace and scale the input data array and to produce a de-interlaced and scaled output version of the input data array.

De-interlacing data arrays in data processing systems

An apparatus for compositing an output surface () from a plurality of input surfaces () includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces () can be combined into a single secondary surface for provision to the composition processor. When it is determined that two or more input surfaces of the plurality of input surfaces () can be combined into a single secondary surface for provision to the composition processor, the processing circuitry is configured to provide data representing the secondary surface to the composition processor, the data indicating the input surfaces that contribute to the secondary surface.

Method of and apparatus for providing an output surface in a data processing system

A method of operating a data processing systemis disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memoryof the data processing system, and reading the data from the memoryin the form of lines.

Data processing systems

In a display controller of a data processing system, when composing two or more input surfaces to generate a composited surface comprising the two or more input surfaces, data indicating a border between different input surfaces in the composited surface is associated with the composited surface. The data indicative of the border between two input surfaces in the composited surface is then used to control subsequent processing, such as compression and/or filtering, of the composited surface.

Display controllers

A display controllercomprises a first display processing corecomprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display, and a first write-out stageoperable to write data of an output surface to external memory, and a second display processing corecomprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display. The display controlleralso comprises an internal data pathfor passing data of an output surface from the first display coreto the second display core

A device comprises a content-processing component operable to perform a content-processing operation. The device comprises a sensor operable to output data indicative of activity of an eyelid of a user of the device. The device comprises a processor configured to process the data output by the sensor, to cause the content-processing operation to be in an enabled state in response to the processing of the data output by the sensor indicating that the eyelid is open by more than an open-eyelid threshold, and to cause the content-processing operation to be in a disabled state in response to the processing of the data output by the sensor indicating that the eyelid is closed by more than a closed-eyelid threshold.

Devices and headsets

A display controller comprises an input stageoperable to read at least one input surface, a composition stageoperable to compose plural input surfaces to generate a composited output surface, an output stageoperable to provide the composited output surface to a display for display, a scaling engineoperable to scale a composited output surface generated by the composition stageand a write-out stageoperable to write a composited and/or scaled output surface to external memory.

In a display controller, output surface data from a composition processing stageis received by and stored in a local latency hiding bufferof a memory write subsystembefore being written out to an external memory. The local bufferof the memory write subsystemsignals when it is 'full', and in response thereto the inputting of output surface data to the local bufferis stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local bufferthat is already present in the local bufferand not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.

Growing community of inventors

Cambridge, United Kingdom

Piotr Chrobak