Taiwan Semiconductor Manufacturing Comp. Ltd.

Pinyen Lin

Sung-Li Wang

Po-Chin Chang

Lin-Yu Huang

Shuen-Shin Liang

Chia-Hung Chu

Huang-Lin Chao

Yuting Cheng

Tzu-Pei Chen

Hung-Yi Huang

Shen-Yang Lee

Harry Chien

Chung-Liang Cheng

Ken-Yu Chang

Hsu-Kai Chang

Wei-Yip Loh

Hsiang-Pi Chang

Hong-Mao Lee

Kuan-Kan Hu

Chuan-Hui Shen

Li-Te S Lin

Li-Zhen Yu

Liang-Yin Chen

Chia-Cheng Chen

Cheng-Ming Lin

Sheng-Tsung Wang

Chansyun David Yang

Tzer-Min Shen

Chun-Hung Wu

Han-Yu Lin

Fu-Ting Yen

Chun-I Tsai

Yan-Ming Tsai

Tze-Chung Lin

Yao-Sheng Huang

Wei-Yen Woon

Yen-Tien Tung

Jhih-Rong Huang

Kan-Ju Lin

Tsun-Jen Chan

Cheng-Wei Lian

Yu-Chia Liang

Kuan-Da Huang

Szu-Hua Chen

I-ming Chang

Chih-Shiun Chou

Shao-An Wang

Szu-Hsian Lee

Che-Chi Shih

Min-Chiang Chuang

Chia-Ling Pai

A method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer; performing a first annealing process to densify the dielectric interfacial layer; overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.

Semiconductor devices and methods of manufacturing thereof

A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.

Isolation structure for semiconductor device

A method for manufacturing a semiconductor device includes: forming a semiconductor stack on a semiconductor substrate in a flat state, the semiconductor stack including sacrificial layer portions and channel layer portions that are alternately stacked over one another; forming source/drain trenches in the semiconductor stack, each of the source/drain trenches penetrating the channel layer portions, the sacrificial layer portions and an upper portion of the semiconductor substrate, and terminating at a lower portion of the semiconductor substrate, so as to form the channel layer portions into channel features and form the sacrificial layer portions into sacrificial features; transforming the semiconductor substrate from the flat state to a bending state; forming source/drain regions in the source/drain trenches, respectively; and reverting the semiconductor substrate from the bending state back to the flat state, so as to induce a strain in the channel features.

Semiconductor device having strained channel and method for manufacturing the same

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

Semiconductor device including stacked via contact and method for manufacturing the same

A semiconductor device includes a semiconductor structure, a conductive nitride feature, a third dielectric feature, and a conductive line feature. The semiconductor structure includes a substrate, two source/drain regions disposed in the substrate, a first dielectric feature disposed over the substrate, a gate structure disposed in the first dielectric feature and between the source/drain regions, a second dielectric feature disposed over the first dielectric feature, and a contact feature disposed in the second dielectric feature and being connected to at least one of the source/drain regions and the gate structure. The conductive nitride feature includes metal nitride or alloy nitride, is disposed in the second dielectric feature, and is connected to the contact feature. The third dielectric feature is disposed over the second dielectric feature. The conductive feature is disposed in the third dielectric feature and is connected to the conductive nitride feature opposite to the contact feature.

Semiconductor device including conductive nitride feature and method of making the semiconductor device

A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.

Semiconductor device with conductive liners over silicide structures and method of making the semiconductor device

A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device with tunable threshold voltage and method for manufacturing the same

A method is provided for forming a contact plug by bottom-up metal growth. In one step, a substrate is etched to form a contact hole that exposes a silicon-containing feature in the substrate. In one step, a silicide layer is formed on the silicon-containing feature. In one step, a metal seed layer is formed over the silicide layer. In one step, a metal contact layer is deposited over the metal seed layer to form the contact plug in the contact hole.

Method for forming a contact plug by bottom-up metal growth

A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

Gate to source drain interconnects

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Hsinchu, Taiwan

Pinyen Lin