Intel Corporation

Pinkesh J Shah

Ren Wang

Christian Maciocco

Herbert H Hum

Zeshan A Chishti

Eric R Delano

Ahmad A Samih

Tsung-Yuan Charlie Tai

Lingdan Zeng

Stephen T Palermo

James W Alexander

Lokpraveen B Mosur

Malay Trivedi

Srihari Makineni

Mohan Nair

Neelam Chandwani

Shrikant M Shah

Rajesh Gadiyar

Buck Gremel

Uzair Qureshi

Shubha Bommalingaiahnapallya

Rany ElSayed

An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Systems, methods, and apparatus for workload optimized central processing units (CPUS)

A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

Efficient data transfer between a processor core and an accelerator

In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Power gating a portion of a cache memory

An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Method and apparatus for optimizing power and latency on a link

Growing community of inventors

Gilbert, AZ, United States of America

Pinkesh J Shah