Cadence Design Systems, Inc.

Pinhong Chen

Qi Wang

Vivek Chickermane

Ankur Gupta

Manish Pandey

Patrick Gallagher

Sandeep Bhatia

Huan-Chih Tsai

Christina Chu

Steven Sharp

Yonghao Chen

Mitchell W Hines

Dongzi Liu

Richard M Chou

Liqun Deng

Chin-Chi Teng

Miao Liu

Yi Qian

Fangfang Li

Yufeng Luo

Deng Pan

Kai-Ti Huang

Wilsin Gosti

Yanhui Wang

Yonghoa Chen

Chin-Chih Chang

Wanshuan Liu

Jackey Z Yan

WenHsing Tsai

Cindy Zhang

Jieqian Yu

Hanqi Yang

Ximing Zhou

Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.

Methods, systems, and computer program products for efficiently implementing a 3D-IC

Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.

Concurrent optimization of 3D-IC with asymmetrical routing layers

Aspects of the present disclosure address systems, methods, and an improved graphical user interface (GUI) for providing interactive macro-cell placement for integrated circuit (IC) design. The method includes causing display of a GUI that includes a display of an IC floor plan comprising multiple macro-cells, The method further includes receiving a user selection of two or more macro-cells from the IC floor plan, and updating the GUI to display layout options for the two or more macro-cells in conjunction with the display of the IC floor plan. Each layout option specifies an arrangement of the two or more macro-cells. In response to a user selection of a layout option, the display of the IC floor plan is updated by modifying a placement of the two or more macro-cells in accordance with the selected layout option.

Graphical user interface for interactive macro-cell placement

Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.

Method, system, and computer program product for implementing electronic designs with automatically generated power intent

Electronic design automation systems and methods are presented for top-down timing budget flow in master-clone scenarios. In some embodiments, different instances of a master-clone block within an integrated circuit design are associated with different constraint files. The different constraint files are based on the different connections of each instance with elements of the integrated circuit design as well as the shared structure of the master-clone block. A top-down timing budget flow may then be generated based on the differing constraint files, and the integrated circuit design may be modified based on this analysis prior to generation of physical devices based on the design.

Multi-instantiated block timing optimization

A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a first register occurrence. A reduced netlist spans the regional circuitry and the modeled external circuitry. Embodiments optimize the reduced netlist under design constraints applicable to the full circuit design. Changes to the original circuit design made by the optimization are tangibly saved as engineering change orders. The optimization process may be applied to other regions, including via parallel execution by multiple processors. Conventional design bottlenecks may be bypassed for greatly improved quality of results and reduced turnaround time.

Reverse interface logic model for optimizing physical hierarchy under full chip constraint

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Method and mechanism for implementing electronic designs having power information specifications background

A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.

High level IC design with power specification and power source hierarchy

Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

Method and apparatus for power consumption optimization for integrated circuits

To estimate path delays within an IC, a serial database is first created to hold and read out RC extraction data for nets within the IC in an order in which the RC extraction data will be needed when estimating path delays. Thereafter, as the RC extraction data is sequentially read out of the database for each net, the path delay though each section of the net is computed and added to the estimated path delay for each signal path including that net section. The RC extraction data for each net is accessed and accessed only once, thereby minimizing the processing time needed to perform timing analysis by minimizing hard disk read accesses when the RC extraction database resides on a hard disk.

Method of estimating path delays in an IC

Crosstalk noise peaks in output signals of nets of an integrated circuit layout design are estimated by first processing the design to estimate resistances and capacitances of the nets. The design is then processed to identify each aggressor net having at least one section that is proximate to a section of a victim net. A separate aggressor model is then generated for each proximate aggressor net section, the aggressor model including a current source and a capacitor. The design is then processed to identify each victim net that is proximate any aggressor net and a separate crosstalk model is generated for each identified victim net. The crosstalk model for each victim net includes the victim net's estimated resistances and capacitances and incorporates the aggressor model of each aggressor net section that is proximate to a section of the identified victim net. The crosstalk model for each identified victim net is then evaluated to determine a response to a signal applied as input to the victim net of a victim net output signal. The peak crosstalk noise in each identified victim net is estimated based on the response of the net's output signal.

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Saratoga, CA, United States of America

Pinhong Chen