Advanced Micro Devices Corporation

Shanghai Iluvatar Corex Semiconductor Co., Ltd.

Xgi Technology Inc.

Nanjing Iluvatar Corex Technology Co., Ltd.

Pingping Shao

ZhongXiang Luo

XuHong Xiong

Jinshan Zheng

ChenBin Wang

Yongliu Wang

YunXiao Zou

Yile Sun

Jiejun Chen

Guofang Jiao

Chun Yu

Linglan Zhang

Haihua Zhai

Jianbo Zhang

A hardware architecture that may include: a host, a frontal engine, a parietal engine, a renderer engine, an occipital engine, a temporal engine, and a memory. The frontal engine may obtain a 5D tensor from the host and divide it into several groups of tensors. These groups of tensors may be sent or transmitted to the parietal engine, and the parietal engine may take the groups of tensors to further divide them into several tensors. The parietal engine may send these tensors to the renderer engine for execution and may send a partial amount of tensors to the occipital engine. The occipital engine may accumulate the partial amount of tensors and may execute them. The occipital engine may send the output feature as the final tensor to the temporal engine. The temporal engine may compress the final tensor before storing or saving it to the memory.

Hardware architecture for accelerating artificial intelligent processor

A data reuse method based on a convolutional neural network accelerator includes a tile scanning module receiving command information of a command module, the command information comprising a size of a CNN job to be divided into tile blocks; a tile scanning module according to a tile. The size of the tile generates the coordinates of the tile block and sends it to the memory request module; the memory request module generates a memory read request and sends the memory read request to the memory module; the memory module sequentially returns the tile block data to the input activation In the weight buffer unit, the input activation weight buffer unit saves the received tile block data to implement data reuse and transmits the received tile block data to the calculation processing unit PE.

Data reuse method based on convolutional neural network accelerator

A hierarchical sparse tensor compression method based on artificial intelligence devices, in DRAM, not only saves the storage space of the neuron surface, but also adds a meta-surface to the mask block. When reading data, the mask is first read, then the size of the non-zero data is calculated, and only these non-zero data are read to save DRAM bandwidth. In the cache, only non-zero data is stored, so the required storage space is reduced. When processing data, only non-zero data is used. The method uses a bit mask to determine if the data is zero. There are three levels in the hierarchical compression scheme: tiles, lines, and points, reading bitmasks and non-zero data from DRAM, and saving bandwidth by not reading zero data. When processing data, if their bit mask is zero, the tile data may be easily removed.

Hierarchical sparse tensor compression method in artificial intelligent devices

A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

System and method for managing data in a ring buffer

Ring buffer including a preload buffer

A method and system for clearing depth and color buffers in a real time graphics rendering system. The method and system are able to improve both depth and color buffer clearing. The method and system may utilize a frame flag, a depth clearing module, and a fast color and frame flag clearing module. The system assigns a frame flag to each pixel, which is used to determine whether the current Z value for the pixel is valid. The frame flag may be attached to Z value in the depth buffer. Instead of filling entire depth and color buffers with background values, the system only fills the holes that were not drawn in the previous frame. The fast color and frame flag clearing module traverses a rectangular area, tile by tile, where a tile is a block of pixels, to determine whether each pixel is background by checking the frame flags that are read from the depth buffer. If at least one pixel of a tile is background, the module updates those pixels' color with background color by sending requests to memory interface.

System and method for clearing depth and color buffers in a real-time graphics rendering system

Growing community of inventors

Sunnyvale, CA, United States of America

Pingping Shao