Texas Instruments Corporation

Pinghai Hao

Sameer P Pendharkar

Xiaoju Wu

Dong Seup Lee

Binghua Hu

Imran Khan

Shanjen Pan

Amitava Chatterjee

Marie Denison

Jungwoo Joh

Seetharaman Sridhar

Jozef C Mitros

James Robert Todd

Jarvis Benjamin Jacobs

Fan-Chi Hou

Fuchao Wang

Joe R Trogolo

Weidong Tian

Duofeng Yue

Yoshikazu Kondo

Qingfeng Wang

Sameer P Pendharker

Philip Leland Hower

Eric W Beach

Keith M Jarreau

Victor Ivanov

Zafar Imam

Tsutomu Kubota

Larry B Anderson

Fan Chi Hou

Yvonne Patton

Eric William Beach

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

Gallium nitride transistor with a doped region

A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

HEMT wafer probe current collapse screening

In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.

Transistor with multiple GaN-based alloy layers

An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

High voltage CMOS with triple gate oxide

An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

Recessed solid state apparatuses

In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.

Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

Single photomask high precision thin film resistor

An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

Low cost transistors

Growing community of inventors

Plano, TX, United States of America

Pinghai Hao