Apex Semiconductor

Pingchun Chiang

Alfred Yeung

Suresh Subramaniam

Pravin Chingudi

Minkyu Kim

Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA. DMC can determine or predict another operating condition(s) associated with the design based on the operating condition and the trained model.

Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction

A corner prediction system applies data generated through discrete process, voltage, and temperature (PVT) corner prediction to achieve highly accurate continuous corner prediction coverage. Embodiments of the corner prediction system can be trained to generate accurate performance metric prediction for a continuous range of PVT corners within a design space given a set of available pre-trained PVT corners. The corner prediction system can address the need to provide accurate continuous timing prediction coverage of design operating conditions (represented by PVT corners) through the availability of discrete PVT corners.

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San Jose, CA, United States of America

Pingchun Chiang