Taiwan Semiconductor Manufacturing Comp. Ltd.

Ping-Yin Liu

Xin-Hua Huang

Lan-Lin Chao

Chia-Shiung Tsai

Yuan-Chih Hsieh

Xiaomeng Chen

Yeur-Luen Tu

Hung-Hua Lin

Jung-Huei Peng

Hsun-Chung Kuang

Chun-Wen Cheng

Yeong-Jyh Lin

Szu-Ying Chen

Yen-Chang Chu

Kuan-Liang Liu

Jen-Cheng Liu

Chung-Yi Yu

Shang-Ying Tsai

Hsin-Ting Huang

Pin-Nan Tseng

Li-Cheng Chu

Dun-Nian Yaung

Chen-Jong Wang

Chang-Ming Wu

Shih-Wei Lin

Tzu-Jui Wang

Chih-Hui Huang

Ming-Tung Wu

Cheng-Tai Hsiao

Ru-Liang Lee

Yao-Te Huang

Bruce C S Chou

Jung-Kuo Tu

Hung-Chia Tsai

Kuo Liang Lu

Chang-Chen Tsao

Tsung-Te Chou

Alexander Kalnitsky

Cheng-Yuan Tsai

Chih-Ming Chen

Chi-Ming Chen

Lee-Chuan Tseng

Kai-Wen Cheng

Calvin Yi-Ping Chao

Yu-Hsing Chang

Ching-Hung Wang

Xin-Chung Kuang

Hsin-Chang Lee

Jhy-Jyi Sze

Chih-Chiang Tu

Yun-Yue Lin

Chih-Cheng Lin

Chun-Lang Chen

Yung-Lung Lin

Jong-Yuh Chang

Chue San Yoo

Yan-Chih Lu

Da-Hsiang Chou

Che Ying Hsu

Li-Chen Chu

H T Huang

Lan-Lin

Chia-Chiung Tsai

The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

Deposition system for high accuracy patterning

A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Integrate rinse module in hybrid bonding platform

In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.

Simultaneous bonding approach for high quality wafer stacking

A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

MEMS device having a metallization structure embedded in a dielectric structure with laterally offset sidewalls of a first portion and a second portion

A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Dual facing BSI image sensors with wafer level stacking

In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

Patterning a transparent wafer to form an alignment mark in the transparent wafer

The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.

Apparatus for bond wave propagation control

Simultaneous bonding approach for high quality wafer stacking applications

An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.

Low contamination chamber for surface activation

Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer

Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

Method for alignment, process tool and method for wafer-level alignment

Growing community of inventors

Yonghe, Taiwan

Ping-Yin Liu