Altera Corporation

Ping Xiao

Weiying Ding

Leo Min Maung

William W Bereza

Mohsen Moussavi

Weiyding Ding

Myron Wai Wong

Mario E Guzman

An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

Methods and apparatus for configuring and reconfiguring a partial reconfiguration region

A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

3D field programmable gate array system with reset management and method of manufacture thereof

3D field programmable gate array system with reset manufacture and method of manufacture thereof

Methods and systems for detection and monitoring of power supply voltage and voltage reference circuitry are provided. In one embodiment of the invention, a first signal is set to be proportional to a power supply voltage in response to a determination from control circuitry that an output voltage of bandgap voltage reference circuitry is less than a first threshold voltage. The first signal is set to a logic low level in response to a determination from control circuitry that the output voltage of the bandgap voltage reference circuit is greater than the first threshold voltage, wherein the first threshold voltage is less than a bandgap reference voltage. A value of a reset signal is determined based at least in part on the first signal.

Methods and systems for voltage reference power detection

An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.

Thermometer-code-to-binary encoders

Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.

Power-on-reset circuitry

A sensing circuit for comparing current flow through a reference resistance with current flow through a resistive device under test (DUT) such as a fuse. The sensing circuit includes a comparator having a first PMOS transistor and a first NMOS transistor connected in series between a first input and a first node and a second PMOS transistor and a second NMOS transistor connected in series between a second input and the first node. The first PMOS and NMOS transistors are cross-coupled with the second PMOS and NMOS transistors. Specifically, a first output is connected to the first node to the gates of the second PMOS and second NMOS transistors and a second output is connected to the second node and to the gates of the first PMOS and first NMOS transistors. The reference resistance is connected to one of the inputs and the DUT is connected to the other input.

Sensing circuit

Circuits, methods, and systems for implementing an Analog to Digital Converter (ADC) in an Integrated Circuit (IC) are provided. An IC includes an analog modulator, a digital filter coupled to the analog modulator, and a decimator coupled to the digital filter. The analog modulator includes one or more discrete integrators and a feedback path. A first discrete integrator from the one or more discrete integrators is operable to receive an analog input of the ADC. The feedback path couples an output of the analog modulator to at least one of the one or more discrete integrators. Further, the decimator is operable to produce the output of the ADC, and the IC is operable to receive an IC configuration file that specifies how the discrete integrators are connected in the analog modulator, parameters of the digital filter, and parameters of the decimator.

Integrated circuit with configurable analog to digital converter

Circuitry on an integrated circuit is provided that may be used to program fuses such as polysilicon fuses. Fuse programming may be performed using an elevated power supply voltage. Other circuitry on the integrated circuit may be powered using a standard power supply voltage that is less than the elevated power supply voltage. Fuse sensing may be performed using the standard power supply voltage. A control block may be used to produce a fuse programming control signal. Power-on-reset circuitry may monitor the elevated power supply voltage and may produce a corresponding elevated power supply voltage power-on-reset signal indicative of whether the elevated power supply voltage is valid. The power-on-reset circuitry may also produce a standard power supply power-on-reset signal indicative of whether the standard power supply voltage is valid. The power-on-reset signals may be used in controlling fuse programming and fuse sensing.

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East Palo Alto, CA, United States of America

Ping Xiao