Silicon Storage Technology, Inc.

Xicor Corporation

Sun Microsystems, Inc.

Ping Wang

Isao Nojima

Ching S Jeng

Juei-Chi Hsu

John M Caywood

William H Owen

Joseph Drori

James M Jaffe

Jeffrey Sung

Ching-Shi Jeng

Daniel C Guterman

Bing Yeh

Ching-Shi Jenq

Hung Q Nguyen

Tao-Ying Yau

Xiaozhen Guo

Mahesh Krishnamurthy

A sense amplifier pulse shaping circuit maintains a relationship between a sense amplifier enable signal and a sense amplifier equalization enable signal while disabling equalization prior to evaluation and disabling evaluation prior to equalization. In some embodiments of the present invention, a sense amplifier pulse shaper circuit generates a sense amplifier equalization control signal and a sense amplifier enable signal. The sense amplifier equalization control signal has a rising transition effectively earlier than the rising transition of the sense amplifier enable signal. The sense amplifier enable signal has a falling transition effectively earlier than the falling transition of the sense amplifier equalization control signal. The sense amplifier equalization signal is discharged into the sense amplifier enable signal.

Pulse shaper circuit for sense amplifier enable driver

A system for minimizing the effect of clock skew in a precharge circuit includes a switch coupled between an input to the precharge circuit and a global bitline; and a control circuit coupled to a precharge component and the switch. The control circuit determines whether the switch and the precharge component are activated and the control circuit receives feedback from the switch. A method of minimizing the effect of clock skew in a precharge circuit includes controlling whether an input signal outputting a first signal and a second signal from the precharge circuit; controlling the outputting of the second signal from the precharge circuit based on a clock signal, a select signal, and a dynamic signal.

Minimizing the effect of clock skew in precharge circuit

A sensing circuit for sensing the multiple states of a selected memory cell of a floating gate memory device is disclosed. The sensing circuit has a first voltage amplifier which generates a first output voltage, and a plurality of current amplifiers which receive the first output voltage and generate a plurality of first output currents in response thereto. The circuit also comprises a dummy cell, a second voltage amplifier connected thereto for generating a second output voltage. A second current amplifier receives the second output voltage and generates a plurality of second output currents in response thereto. Each of a plurality of inverters receives one of the first and one of the second output currents, and generates an output. The output of the plurality of invertors are supplied to a decoder to generate a decoded signal representative of the plurality of states of the selected memory cell.

Sensing circuit for a floating gate memory device having multiple levels

A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the source region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate. Programming is accomplished by electrons from the drain migrating through the channel region underneath the control gate and then by abrupt potential drop injecting through the first insulating layer into the floating gate.

Method of operating a single transistor non-volatile electrically

A solid state peripheral storage device receives an LSN address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units which are made out of solid state floating gate storage cells. In addition, a microsequencer controls the operation of the translation of the mapping of the LSN to PSN. Through the use of the mapping of LSN to PSN, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, the microsequencer has error recovery routines to further enhance the reliability of the peripheral device.

Solid state peripheral storage device

An electrically programmable and erasable floating gate memory device has two substantially identical sections. Each section has a plurality of column address lines, a plurality of row lines and a plurality of source lines. A first plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same first row line and its source connected to the same first source line. A second plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same second row line, different from the first row line, and its source connected to the same first source line. Associated with each section is a plurality of bit latches, one for each column. Reprogramming data is stored in the bit latches. Data from the bit latches of one section are stored in the first plurality of floating gate memory cells. Data from the bit latches of the other section are stored in the second plurality of floating gate memory cells.

Floating gate memory array with latches having improved immunity to

A sensing circuit for a floating gate memory device is disclosed. The sensing circuit has a first voltage amplifier which generates a first output voltage, and a current amplifier which receives the first output voltage and generates a first output current in response thereto. The first voltage amplifier has a control transistor which generates a first output voltage in response to the memory device being in one state and a second output voltage in response to the memory device being in another state. The circuit also comprises a dummy cell, a second voltage amplifier connected thereto for generating a second output voltage. A second current amplifier receives the second output voltage and generates a second output current in response thereto. A comparator receives the first and second output currents, compares them, and generates an output indicative of the state of the memory device.

Sensing circuit for a floating gate memory device

A solid state peripheral storage device in compliance with the PCMCIA standard provides data signals on either 16 data signal lines or 8 data signal lines. The device has a plurality of even number of substantially identical memory integrated circuit chips divided into two groups. Each of the memory integrated circuit chips provides 8 data signal lines divided into two groups of 4 data signal lines. One of the group of 4 data signal lines from one of the group of memory chips is grouped with one of the 4 data signal lines from the other group of memory chips to form a first group of 8 contiguous bus of data signal lines. The other group of 4 data signal lines from one group of memory chips is also collected with 4 data signal lines from the other group of memory chips to form a second group of 8 contiguous data signal lines. The two groups of 8 contiguous data signal lines are grouped together to form the bus of 16 data signal lines.

Solid state memory device capable of providing data signals on 2N data

An electrically programmable and erasable floating gate memory array device is disclosed. The array has a plurality of column address lines, a plurality of row address lines, and a plurality of common source lines. Each of the memory cells has one terminal connected to one of the column address lines, another one connected to one of the row address lines, and a third connected to one of the common source lines. By appropriate selection circuit, a high voltage source can be connected to either the row address line to effect erasure of charges on the floating gate of the memory cells connected to the selected row address line or to the common source line to selectively program the memory cells connected to the associated common source line. In this manner, write disturbance can be limited.

Floating gate memory array device having improved immunity to write

In the present invention a write protection circuit capable of being used in a memory card is disclosed. The write protection circuit receives an externally supplied write protect signal and generates a protection signal for use with an associated electrically alterable non-volatile memory. The write protection circuit has two non-volatile storage registers, each storing a single bit. Logic means receives a bit from a first register and passes the externally supplied write protect signal as the internally generated protection signal when the bit is in a '1' state. When the bit is in another state, the signal from the second register is used as the protection signal.

Write protection circuit for use with an electrically alterable

A charge pump has a chain of diode connected MOS transistors to generate a high voltage output. Each of the serially connected MOS transistors has a capacitor with one end connected to the input of one of the transistors. A ring oscillating circuit receives an enable signal and generates a plurality of oscillating signals. Each oscillating signal has the same frequency and is supplied to the second end of a capacitor. Between each capacitor the ring oscillating circuit has an inverter which inverts the supplied oscillating signal. Thus, immediately adjacent capacitors are provided with an inverse oscillating signal. In this manner, the charge pump can be operated at a high frequency, drawing smoother current from the power supply, with greater capacitive loading distributed unto each stage of the oscillator. Finally, breakdown prevention needs only applied to the anode of the last diode.

High frequency voltage multiplier for an electrically erasable and

A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

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Saratoga, CA, United States of America

Ping Wang