Intel Corporation

D.e. Shaw Research, LLC

Lntel Corporation

Ping Tak Peter Tang

Brannon J Batson

Ron Dror

J P Grossman

Theodore Kubaska

Simon C Steely, Jr

Robert Dale Cavin

Jong Soo Park

Kent D Glossop

Kermin Elliott Fleming, Jr

John R Harrison

Vladimir S Petrov

A method for managing flow of particles into an array of pairwise-point-interaction-module includes receiving a first set of particles into a first queue. The first set is a proper subset of a second set of particles that comprises all particles that are to be passed into an array of pairwise-point-interaction-modules during a current time period. Prior to having received all particles from the second set, particles from the first set are allowed to pass from the first queue into the array.

Suppressing interaction between bonded particles

A method comprising causing a simulation machine for molecular dynamic simulation to determine that a topological distance that separates two particles is less than a threshold. The simulation machine includes nodes connected by a network. The nodes collectively representing a volume with each node corresponding to a portion of the simulation space. A topological relationship between the nodes corresponds to spatial relationship thereof in the simulation space. The simulation volume is occupied by particles that interact with each other. The two particles are among these particles. The simulation volume includes node boxes, each of which is handled by one of the nodes. Each of the nodes is implemented as an application specific integrated circuit that includes a combination of first and second hardware elements. The first hardware elements are especially designed to perform pairwise interactions. The second hardware elements operate to provide potentially interacting particles to the first hardware elements.

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs.

Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features

Fourier transform computation for distributed processing environments is disclosed. Example methods disclosed herein to compute a Fourier transform of an input data sequence include performing first processing on the input data sequence using a plurality of processors, the first processing resulting in an output data sequence having more data elements than the input data sequence Such example methods also include performing second processing on the output data sequence using the plurality of processors, the output data sequence being permutated among the plurality of processors, each of the processors performing the second processing on a respective permutated portion of the output data sequence to determine a respective, ordered segment of the Fourier transform of the input data sequence.

Fourier transform computation for distributed processing environments

A new function for calculating the reciprocal residual of a floating-point number X is defined as recip_residual(X)=1&#x2212;X*recip(X), where recip(X) represents the reciprocal of X. The function may be implemented using a fused multiply-add unit in a processor. The reciprocal value of X, recip(X), may be obtained from a lookup table. The recip_residual function may help reduce the latency of many multiplicative functions that are based on products of multiple numbers and can be expressed in simple terms of functions on each individual number (e.g., log(U*V)=log(U)+log(V)).

Method and apparatus for performing multiplicative functions

There is disclosed method, software and apparatus for evaluating a function f in a computing device using a reduction, core approximation and final reconstruction stage. According to one embodiment of the invention, an argument reduction stage uses an approximate reciprocal table in the computing device. According to another embodiment, an approximate reciprocal instruction I is operative on the computing device to use the approximate reciprocal table such that the argument reduction stage provides that&#x2014;C:=I(X) and R:=X&#xd7;C&#x2212;1, the core approximation stage provides that p(R) is computed so that it approximates f(1+R), and the final reconstruction stage provides that T=f(1/C) is fetched and calculated if necessary, and f(X) is reconstructed based on f(X)=f([1/C]&#xd7;[X&#xd7;C])=g(f(1/C), f(1+R)).

Methods and apparatus for fast argument reduction in a computing system

An apparatus and method for creating lookup tables of approximate floating-point quotients which exactly represent the underlying value, within the range of the specified precision. The lookup tables are created without any extraneous data beyond what is needed and also without sacrificing numerical accuracy, and may be creating for any radix.

Apparatus and method for remainder calculation using short approximate floating-point quotient

Apparatus and methods are provided for an improved on-the-fly rounding technique for digit-recurrence algorithms, such as division and square root calculations. According to one embodiment, only two forms of an intermediate result of an operation to be performed by a digit-recurrence algorithm are maintained. A first form is maintained in a first register and a second form is maintained in a second register. Responsive to receiving digits 1 to L&minus;2 of the intermediate result from a digit recurrence unit, where L represents a number of digits that satisfies a predetermined precision for the operation, both forms of the intermediate result are updated by register swapping or concatenation under the control of load and shift control logic and on-the-fly conversion logic. Then, a rounded result is generated by determining digits d and d and appending a rounded last digit to the appropriate form of the intermediate result.

Economical on-the-fly rounding for digit-recurrence algorithms

A method suitable for calculating an expression having the form (A/B) by a processor that features separate sets of floating point units which can operate in parallel for greater speed of execution. The processor issues instructions to determine an approximate reciprocal R of a first variable B. Further instructions are issued to raise a second variable to the power of a third variable K by a first set of arithmetic units of the processor, where the second variable is a function of the approximate reciprocal R . Still further instructions are issued to calculate a polynomial q at a fourth variable delta by a second set of arithmetic units of the processor. The fourth variable delta is also a function of the approximate reciprocal R . Finally, one or more instructions are issued to multiply the calculated polynomial by the second variable, having been raised to the power of the third variable, to yield (A/B) .

Growing community of inventors

Edison, NJ, United States of America

Ping Tak Peter Tang