Taiwan Semiconductor Manufacturing Comp. Ltd.

Ping-Pang Hsieh

Chih-Ming Lee

Yu-Chu Lin

Shih-Lu Hsu

Keng-Ying Liao

Chiang-Ming Chuang

Su-Yu Yeh

Yen-Jou Wu

Hsin-Hui Lin

Yu-Liang Wang

Hsin-Chi Chen

Kun-Tsang Chuang

Chih-Hsun Lin

Chia-Ming Pan

Jyun-Guan Jhou

Kuan-Wei Su

Szu-Hsien Lu

Chia Hsing Huang

Chun Yu Huang

Pei-Chi Ho

Shiu-Ko JangJian

Shang-Yen Wu

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Polysilicon removal in word line contact region of memory devices

A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.

Floating gate isolation

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

Methods for improving interlayer dielectric layer topography

A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.

Floating gate isolation and method for manufacturing the same

Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.

A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region.

Formation of semiconductor device with resistors having different resistances

A method comprises forming a gate stack over a substrate, applying an oxygen flush process to the gate stack, forming a uniform oxide layer on the gate stack as a result of performing the step of applying the oxygen flush process and removing the uniform oxide layer through a pre-clean process.

Apparatus and method for memory device

A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.

Method for forming semiconductor device structure

Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

Gate structure with multiple spacers

A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region.

Silicide process using OD spacers

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.

Semiconductor device structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

Gate structure with multiple spacer and method for manufacturing the same

A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate.

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Tainan, Taiwan

Ping-Pang Hsieh