Ememory Technology Inc.

Ping-Lung Ho

Lun-Chun Chen

Chun-Hung Lin

Hsin-Ming Chen

Meng-Yi Wu

Wei-Zhe Wong

Jiun-Ren Chen

Tsao-Hsin Yang

An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Antifuse-type one time programming memory cell with gate-all-around transistor

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Antifuse-type one time programming memory with forksheet transistors

An OTP memory cell for a PUFF technology includes a first select transistor, a first antifuse transistor and a second antifuse transistor. A first drain/source terminal of the first select transistor is connected with a bit line. A gate terminal of the first select transistor is connected with a word line. A gate terminal of the first antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the first antifuse transistor are connected with a first antifuse control line. A gate terminal of the second antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the second antifuse transistor are connected with a second antifuse control line.

One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method

An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

One time programming memory cell with fin field-effect transistor using physically unclonable function technology

An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Antifuse-type one time programming memory cell and cell array structure with same

An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line.

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Hsinchu, Taiwan

Ping-Lung Ho