Microsoft Technology Licensing, LLC

Ping Lu

Minhan Chen

Shaishav A Desai

Bupesh Pandita

Charles Walter Boecker

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.

Digital phase-locked loops (PLL) including closed-loop time-to-digital converter (TDC) gain calibration circuits and related methods

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

Time-to-digital converters (TDC) employing a single-stage delay pair and noise shaping for wide input range and reduced quantization noise in a phase-locked loop (PLL)

A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.

Phase interpolator (PI) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods

A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the digitally controlled oscillator (DCO) to correct for the phase/frequency difference to synchronize the generated signal with the reference signal. In an aspect, an adaptive TDC circuit generates a first digital indication in a coarse mode when the offset time is above a threshold and generates a second digital indication in a fine mode when the offset time is below the threshold. The first digital indication and the second digital indication each comprise a same number of bits, and the first digital indication is normalized to the second digital indication for the digital output of the adaptive TDC circuit. A fractional bit may be employed to compensate for a quantization error.

Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods

In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.

Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods

A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.

Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods

A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system further includes control logic configured to: (1) at least partially discharge a first pre-charged capacitive load in response to a signal output by the phase interpolator based on the calibration code, and (2) at least partially discharge a second pre-charged capacitive load in response to a reference signal associated with the phase interpolator. The system further includes a feedback path configured to provide feedback to the calibration stage to allow for a modification of the calibration code, where the feedback is dependent on a first voltage provided by the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load.

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Ping Lu