Taiwan Semiconductor Manufacturing Comp. Ltd.

Ping-Lin Yang

Cheng-Chung Lin

Ming-Zhang Kuo

Sang Hoo Dhong

Osamu Takahashi

Sa-Lly Liu

Fu-Lung Hsueh

Jun-De Jin

Ya-Chen Kao

Chun-Jung Lin

Tong-Chern Ong

Chien-Min Lin

Jimmy Hsiao

Chung-Cheng Chou

Hsin-Hsin Ko

Jia-Rong Hsu

A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Contactless communications using ferromagnetic material

An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

Electron beam lithography methods including time division multiplex loading

A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.

Clock regenerator

A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the mirror array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.

Charged particle lithography system with a long shape illumination beam

The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

Electron beam lithography systems and methods including time division multiplex loading

A package comprises a die stack having at least two stacked dies coupled for contactless communications with each other. At least one of the stacked dies has a substrate joined to its major face. The substrate has a plurality of conductive traces in or on the substrate for conducting power to the dies and for conducting heat from the dies. At least one conductive pillar is joined to at least one of the conductive traces on at least a first edge of the substrate, for conducting power to the at least one die and for conducting heat from the at least one die.

3D IC configuration with contactless communication

Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.

Conditional cell placement

A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.

Growing community of inventors

Tianzhong, Taiwan

Ping-Lin Yang